Síntese de unidades de controlo descritas por grafos dum esquema hierárquicos

• Autor(a) principal: Sklyarov, Valery
• Data de Publicação: 1996
• Outros Autores: Rocha, António Adrego da
• Tipo de documento: Artigo
• Idioma: por
• Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
• Texto Completo: https://proa.ua.pt/index.php/revdeti/article/view/19863

This paper discusses Hierarchical Graph-Schemes that can be efficiently used in order to describe a behaviour of control units. The approach to be considered allows to synthesis the final scheme built from programmable logic devices. However it can be also applied to schemes constructed from arbitrary elements. The control device is modelled as a finite state machine with a stack memory which makes it possible to support hierarchical ordering of operations to be performed. Both Moore and Mealy machines are being considered. The process of synthesis is divided into the following steps: converting a hierarchical graph-scheme to a structural table; state encoding; micro operation assignment and designing the final scheme. A special attention paid to synchronisation problem. The approach combines finite state machines theory with object oriented programming which allows control units to be designed with new facilities, such as: extensibility, flexibility and reuse. The techniques use predefined frames and basic schemes (templates) as far as possible.