Desenvolvimento de estrutura de controle para paralelismo de inversores aplicados em fontes ininterruptas de energia
Autor(a) principal: | |
---|---|
Data de Publicação: | 2018 |
Tipo de documento: | Dissertação |
Idioma: | por |
Título da fonte: | Repositório Institucional Manancial UFSM |
Texto Completo: | http://repositorio.ufsm.br/handle/1/16148 |
Resumo: | This master's thesis proposes a control structure for inverters parallelism on uninterruptible power supply (UPS) modules with low line impedance characteristics. The structure is based on instantaneous current sharing (ICS), by exchanging information between modules through a communication bus. However, the system requires lower communication rates than others ICSs methods, and in addition, presents greater tolerance to output voltage measurement errors. In this system, one module act as a master, generating the synchronism of the voltage references, besides transmitting to the modules its output voltage measurement and LC filter inductor current. The slave modules, as well as the master, execute a voltage control loop and a current control loop, however, they use the master module measurement as a reference to generate errors coefficients that will be used to correct their own measurements. Using these coefficients, the relative measurement errors between the modules are eliminated. The coefficients are updated with each transmission of the master, whose transmission occurs at every 10 periods of voltage control loop sampling. In addition, the modules use a virtual impedance inserted in the circulating current, whose virtual impedance modifies the amplitude of the voltage reference of these, whenever there is difference between the currents of the slaves with respect to the master. This type of virtual impedance has the advantage that it does not affect the regulation of the output voltage. A system with two 2 kVA modules is designed and implemented. Simulation results are obtained with the detailed analysis of the structure. Finally, experimental results are obtained to validate the proposed structure. |
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2019-04-11T11:55:00Z2019-04-11T11:55:00Z2018-08-30http://repositorio.ufsm.br/handle/1/16148This master's thesis proposes a control structure for inverters parallelism on uninterruptible power supply (UPS) modules with low line impedance characteristics. The structure is based on instantaneous current sharing (ICS), by exchanging information between modules through a communication bus. However, the system requires lower communication rates than others ICSs methods, and in addition, presents greater tolerance to output voltage measurement errors. In this system, one module act as a master, generating the synchronism of the voltage references, besides transmitting to the modules its output voltage measurement and LC filter inductor current. The slave modules, as well as the master, execute a voltage control loop and a current control loop, however, they use the master module measurement as a reference to generate errors coefficients that will be used to correct their own measurements. Using these coefficients, the relative measurement errors between the modules are eliminated. The coefficients are updated with each transmission of the master, whose transmission occurs at every 10 periods of voltage control loop sampling. In addition, the modules use a virtual impedance inserted in the circulating current, whose virtual impedance modifies the amplitude of the voltage reference of these, whenever there is difference between the currents of the slaves with respect to the master. This type of virtual impedance has the advantage that it does not affect the regulation of the output voltage. A system with two 2 kVA modules is designed and implemented. Simulation results are obtained with the detailed analysis of the structure. Finally, experimental results are obtained to validate the proposed structure.Esta dissertação de mestrado propõe uma estrutura de controle para paralelismo de inversores em fontes ininterruptas de energia (UPS – Uninterruptible Power Supplie) modulares, com características de baixa impedância de conexão. A estrutura proposta é baseada no compartilhamento instantâneo da corrente de carga (ICS – Instantaneous Current Sharing), por meio da troca de informações entre os módulos através de um barramento de comunicação. Entretanto, este sistema requer taxas de comunicação menores que os métodos ICSs convencionais, além de apresentar maior tolerância à erros de medidas da tensão de saída. Neste sistema, um dos módulos atua como mestre gerando o sincronismo das referências, além de transmitir aos módulos sua medida de tensão de saída e corrente do indutor do filtro LC. Os módulos escravos, assim como o mestre, executam uma malha de tensão e uma malha de corrente, contudo, usam a medida do mestre como referência para gerar coeficientes que serão utilizados para corrigir suas próprias medidas. Empregando-se esses coeficientes, são eliminados os erros de medidas relativas entre os módulos. Os coeficientes são atualizados a cada transmissão do mestre, cuja transmissão ocorre a cada 10 períodos de amostragem da malha de tensão. Além disso, os módulos empregam uma impedância virtual inserida na corrente de circulação, cuja impedância virtual atua modificando a amplitude da referência de tensão destes, sempre que há diferença entre as correntes dos escravos com relação a do mestre. Essa forma de impedância virtual traz a vantagem de não afetar a regulação da tensão de saída. Um sistema com dois módulos de 2 kVA é projetado e implementado. Resultados de simulação são obtidos com a análise detalhada da estrutura. Por fim, resultados experimentais são adquiridos para validar a estrutura proposta.porUniversidade Federal de Santa MariaCentro de TecnologiaPrograma de Pós-Graduação em Engenharia ElétricaUFSMBrasilEngenharia ElétricaAttribution-NonCommercial-NoDerivatives 4.0 Internationalhttp://creativecommons.org/licenses/by-nc-nd/4.0/info:eu-repo/semantics/openAccessParalelismo de inversoresFontes ininterruptas de energiaCompartilhamento instantâneo de cargaEletrônica de potênciaInverter parallelismUninterruptible power suppliesInstantaneous load sharingPower electronicsCNPQ::ENGENHARIAS::ENGENHARIA ELETRICADesenvolvimento de estrutura de controle para paralelismo de inversores aplicados em fontes ininterruptas de energiaControl structure development for parallelism of inverters applied in uninterruptible power suppliesinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/masterThesisRech, Cassianohttp://lattes.cnpq.br/9375639768929991Lazzarin, Telles Brunellihttp://lattes.cnpq.br/2513940350875541Tibola, Jonas Robertohttp://lattes.cnpq.br/7203480799215375http://lattes.cnpq.br/8163647567500044Toebe, Ademir30040000000760064098d57-ec9e-498c-823c-7d3c3559e353dd224d31-ba1d-4613-b77b-6be52480dbca1e7e6c56-472b-4e82-b461-cce3dc6de6b0b7a36d96-4b7d-4012-bdb8-eb78d7fb3b12reponame:Repositório Institucional Manancial UFSMinstname:Universidade Federal de Santa Maria (UFSM)instacron:UFSMORIGINALDIS_PPGEE_2018_TOEBE_ADEMIR.pdfDIS_PPGEE_2018_TOEBE_ADEMIR.pdfDissertação de Mestradoapplication/pdf7260452http://repositorio.ufsm.br/bitstream/1/16148/1/DIS_PPGEE_2018_TOEBE_ADEMIR.pdf65cfe290c6cc6a3ff7db57df03042249MD51CC-LICENSElicense_rdflicense_rdfapplication/rdf+xml; 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dc.title.por.fl_str_mv |
Desenvolvimento de estrutura de controle para paralelismo de inversores aplicados em fontes ininterruptas de energia |
dc.title.alternative.eng.fl_str_mv |
Control structure development for parallelism of inverters applied in uninterruptible power supplies |
title |
Desenvolvimento de estrutura de controle para paralelismo de inversores aplicados em fontes ininterruptas de energia |
spellingShingle |
Desenvolvimento de estrutura de controle para paralelismo de inversores aplicados em fontes ininterruptas de energia Toebe, Ademir Paralelismo de inversores Fontes ininterruptas de energia Compartilhamento instantâneo de carga Eletrônica de potência Inverter parallelism Uninterruptible power supplies Instantaneous load sharing Power electronics CNPQ::ENGENHARIAS::ENGENHARIA ELETRICA |
title_short |
Desenvolvimento de estrutura de controle para paralelismo de inversores aplicados em fontes ininterruptas de energia |
title_full |
Desenvolvimento de estrutura de controle para paralelismo de inversores aplicados em fontes ininterruptas de energia |
title_fullStr |
Desenvolvimento de estrutura de controle para paralelismo de inversores aplicados em fontes ininterruptas de energia |
title_full_unstemmed |
Desenvolvimento de estrutura de controle para paralelismo de inversores aplicados em fontes ininterruptas de energia |
title_sort |
Desenvolvimento de estrutura de controle para paralelismo de inversores aplicados em fontes ininterruptas de energia |
author |
Toebe, Ademir |
author_facet |
Toebe, Ademir |
author_role |
author |
dc.contributor.advisor1.fl_str_mv |
Rech, Cassiano |
dc.contributor.advisor1Lattes.fl_str_mv |
http://lattes.cnpq.br/9375639768929991 |
dc.contributor.referee1.fl_str_mv |
Lazzarin, Telles Brunelli |
dc.contributor.referee1Lattes.fl_str_mv |
http://lattes.cnpq.br/2513940350875541 |
dc.contributor.referee2.fl_str_mv |
Tibola, Jonas Roberto |
dc.contributor.referee2Lattes.fl_str_mv |
http://lattes.cnpq.br/7203480799215375 |
dc.contributor.authorLattes.fl_str_mv |
http://lattes.cnpq.br/8163647567500044 |
dc.contributor.author.fl_str_mv |
Toebe, Ademir |
contributor_str_mv |
Rech, Cassiano Lazzarin, Telles Brunelli Tibola, Jonas Roberto |
dc.subject.por.fl_str_mv |
Paralelismo de inversores Fontes ininterruptas de energia Compartilhamento instantâneo de carga Eletrônica de potência |
topic |
Paralelismo de inversores Fontes ininterruptas de energia Compartilhamento instantâneo de carga Eletrônica de potência Inverter parallelism Uninterruptible power supplies Instantaneous load sharing Power electronics CNPQ::ENGENHARIAS::ENGENHARIA ELETRICA |
dc.subject.eng.fl_str_mv |
Inverter parallelism Uninterruptible power supplies Instantaneous load sharing Power electronics |
dc.subject.cnpq.fl_str_mv |
CNPQ::ENGENHARIAS::ENGENHARIA ELETRICA |
description |
This master's thesis proposes a control structure for inverters parallelism on uninterruptible power supply (UPS) modules with low line impedance characteristics. The structure is based on instantaneous current sharing (ICS), by exchanging information between modules through a communication bus. However, the system requires lower communication rates than others ICSs methods, and in addition, presents greater tolerance to output voltage measurement errors. In this system, one module act as a master, generating the synchronism of the voltage references, besides transmitting to the modules its output voltage measurement and LC filter inductor current. The slave modules, as well as the master, execute a voltage control loop and a current control loop, however, they use the master module measurement as a reference to generate errors coefficients that will be used to correct their own measurements. Using these coefficients, the relative measurement errors between the modules are eliminated. The coefficients are updated with each transmission of the master, whose transmission occurs at every 10 periods of voltage control loop sampling. In addition, the modules use a virtual impedance inserted in the circulating current, whose virtual impedance modifies the amplitude of the voltage reference of these, whenever there is difference between the currents of the slaves with respect to the master. This type of virtual impedance has the advantage that it does not affect the regulation of the output voltage. A system with two 2 kVA modules is designed and implemented. Simulation results are obtained with the detailed analysis of the structure. Finally, experimental results are obtained to validate the proposed structure. |
publishDate |
2018 |
dc.date.issued.fl_str_mv |
2018-08-30 |
dc.date.accessioned.fl_str_mv |
2019-04-11T11:55:00Z |
dc.date.available.fl_str_mv |
2019-04-11T11:55:00Z |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/masterThesis |
format |
masterThesis |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://repositorio.ufsm.br/handle/1/16148 |
url |
http://repositorio.ufsm.br/handle/1/16148 |
dc.language.iso.fl_str_mv |
por |
language |
por |
dc.relation.cnpq.fl_str_mv |
300400000007 |
dc.relation.confidence.fl_str_mv |
600 |
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dc.rights.driver.fl_str_mv |
Attribution-NonCommercial-NoDerivatives 4.0 International http://creativecommons.org/licenses/by-nc-nd/4.0/ info:eu-repo/semantics/openAccess |
rights_invalid_str_mv |
Attribution-NonCommercial-NoDerivatives 4.0 International http://creativecommons.org/licenses/by-nc-nd/4.0/ |
eu_rights_str_mv |
openAccess |
dc.publisher.none.fl_str_mv |
Universidade Federal de Santa Maria Centro de Tecnologia |
dc.publisher.program.fl_str_mv |
Programa de Pós-Graduação em Engenharia Elétrica |
dc.publisher.initials.fl_str_mv |
UFSM |
dc.publisher.country.fl_str_mv |
Brasil |
dc.publisher.department.fl_str_mv |
Engenharia Elétrica |
publisher.none.fl_str_mv |
Universidade Federal de Santa Maria Centro de Tecnologia |
dc.source.none.fl_str_mv |
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