Conversor analógico digital de 10 bits utilizando arquitetura pipeline e tecnologia CMOS

• Autor(a) principal: Silva, Denis Rogério da [UNESP]
• Data de Publicação: 2015
• Tipo de documento: Dissertação
• Idioma: por
• Título da fonte: Repositório Institucional da UNESP
• Texto Completo: http://hdl.handle.net/11449/136044; http://www.athena.biblioteca.unesp.br/exlibris/bd/cathedra/03-03-2016/000859495.pdf
• topic: Conversores analogicos-digitais; Processamento de sinais; Eletronica; Electronics

In this work is presented a analog to digital converter with a resolution of 10 bits and pipeline architecture, which consists in a multi-converter competitive processing steps and the Nyquist Limit type. It is carried out the development of the parties of the converter with greater focus on the analog. Techniques for improving the performance of the converter are presented aiming primarily, minimization of the effects of the offset voltage comparators and low power consumption. An Operational Amplifier with positive feedback is presented aiming an increase of its gain, without compromising on your power consumption. The tests performed were made through simulations using CMOS technology 0.35 μm, voltage supply at 1.8 Volts and switching frequency of transistors of 5 MHz. These tests presented the results of the parties of the converter with the use of the techniques proposed, showing the reach of the expected results