High Temperature Influence on the Trade-off between gm/I-D and f(T) of nanosheet NMOS Transistors with Different Metal Gate Stack

Detalhes bibliográficos
Autor(a) principal: Silva, Vanessa C. P.
Data de Publicação: 2021
Outros Autores: Martino, Joao A., Simoen, Eddy, Veloso, Anabela, Agopian, Paula G. D. [UNESP], IEEE
Tipo de documento: Artigo de conferência
Idioma: eng
Título da fonte: Repositório Institucional da UNESP
Texto Completo: http://dx.doi.org/10.1109/EuroSOI-ULIS53016.2021.9560185
http://hdl.handle.net/11449/237553
Resumo: This work presents an experimental analysis of the trade-off between transistor efficiency (gm/I-D) and unit gain frequency (f(T)) of nanosheet field effect transistors (NSFETs) with different metal gate (MG) stack, considering the influence of high temperature (T), until T=200 degrees C. The results are very promising for both MG stacks. The MG stack (n*) presents a high f(T) about 260 GHz (T=25 degrees C and L=28 nm) and a gm/I-D about 37 V-1 (T=25 degrees C and L=200 nm). The MG stack (m*) also presents very good characteristics, like a f(T) about 252 GHz (T=25 degrees C and L=28 nm) and a gm/In about 35 V-1 (T=25 degrees C and L=200 nm). From the analyses as a function of the inversion coefficient (IC), it was possible to determine that the optimal operation point occurs in the transition from moderate to strong inversion for L=28 nm and it is in strong inversion for long channel devices. In all cases, although the intrinsic voltage gain (Av) is degraded moving away from weak inversion, the degradation was not very pronounced up to the optimal operation point and considering the temperature variation, the Av presents a greater stability at the optimal point than in weak inversion.
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spelling High Temperature Influence on the Trade-off between gm/I-D and f(T) of nanosheet NMOS Transistors with Different Metal Gate StackNanosheets (NS)MOSFETAnalog operationf(T)Transistor EfficiencyThis work presents an experimental analysis of the trade-off between transistor efficiency (gm/I-D) and unit gain frequency (f(T)) of nanosheet field effect transistors (NSFETs) with different metal gate (MG) stack, considering the influence of high temperature (T), until T=200 degrees C. The results are very promising for both MG stacks. The MG stack (n*) presents a high f(T) about 260 GHz (T=25 degrees C and L=28 nm) and a gm/I-D about 37 V-1 (T=25 degrees C and L=200 nm). The MG stack (m*) also presents very good characteristics, like a f(T) about 252 GHz (T=25 degrees C and L=28 nm) and a gm/In about 35 V-1 (T=25 degrees C and L=200 nm). From the analyses as a function of the inversion coefficient (IC), it was possible to determine that the optimal operation point occurs in the transition from moderate to strong inversion for L=28 nm and it is in strong inversion for long channel devices. In all cases, although the intrinsic voltage gain (Av) is degraded moving away from weak inversion, the degradation was not very pronounced up to the optimal operation point and considering the temperature variation, the Av presents a greater stability at the optimal point than in weak inversion.Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)Univ Sao Paulo, LSI PSI USP, Sao Paulo, BrazilIMEC, Leuven, BelgiumSao Paulo State Univ, UNESP, Sao Joao Da Boa Vista, BrazilSao Paulo State Univ, UNESP, Sao Joao Da Boa Vista, BrazilIeeeUniversidade de São Paulo (USP)IMECUniversidade Estadual Paulista (UNESP)Silva, Vanessa C. P.Martino, Joao A.Simoen, EddyVeloso, AnabelaAgopian, Paula G. D. [UNESP]IEEE2022-11-30T13:38:23Z2022-11-30T13:38:23Z2021-01-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject4http://dx.doi.org/10.1109/EuroSOI-ULIS53016.2021.95601852021 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (eurosoi-ulis). New York: Ieee, 4 p., 2021.2330-5738http://hdl.handle.net/11449/23755310.1109/EuroSOI-ULIS53016.2021.9560185WOS:000790181800015Web of Sciencereponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPeng2021 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (eurosoi-ulis)info:eu-repo/semantics/openAccess2022-11-30T13:38:23Zoai:repositorio.unesp.br:11449/237553Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-08-05T18:13:58.390831Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false
dc.title.none.fl_str_mv High Temperature Influence on the Trade-off between gm/I-D and f(T) of nanosheet NMOS Transistors with Different Metal Gate Stack
title High Temperature Influence on the Trade-off between gm/I-D and f(T) of nanosheet NMOS Transistors with Different Metal Gate Stack
spellingShingle High Temperature Influence on the Trade-off between gm/I-D and f(T) of nanosheet NMOS Transistors with Different Metal Gate Stack
Silva, Vanessa C. P.
Nanosheets (NS)
MOSFET
Analog operation
f(T)
Transistor Efficiency
title_short High Temperature Influence on the Trade-off between gm/I-D and f(T) of nanosheet NMOS Transistors with Different Metal Gate Stack
title_full High Temperature Influence on the Trade-off between gm/I-D and f(T) of nanosheet NMOS Transistors with Different Metal Gate Stack
title_fullStr High Temperature Influence on the Trade-off between gm/I-D and f(T) of nanosheet NMOS Transistors with Different Metal Gate Stack
title_full_unstemmed High Temperature Influence on the Trade-off between gm/I-D and f(T) of nanosheet NMOS Transistors with Different Metal Gate Stack
title_sort High Temperature Influence on the Trade-off between gm/I-D and f(T) of nanosheet NMOS Transistors with Different Metal Gate Stack
author Silva, Vanessa C. P.
author_facet Silva, Vanessa C. P.
Martino, Joao A.
Simoen, Eddy
Veloso, Anabela
Agopian, Paula G. D. [UNESP]
IEEE
author_role author
author2 Martino, Joao A.
Simoen, Eddy
Veloso, Anabela
Agopian, Paula G. D. [UNESP]
IEEE
author2_role author
author
author
author
author
dc.contributor.none.fl_str_mv Universidade de São Paulo (USP)
IMEC
Universidade Estadual Paulista (UNESP)
dc.contributor.author.fl_str_mv Silva, Vanessa C. P.
Martino, Joao A.
Simoen, Eddy
Veloso, Anabela
Agopian, Paula G. D. [UNESP]
IEEE
dc.subject.por.fl_str_mv Nanosheets (NS)
MOSFET
Analog operation
f(T)
Transistor Efficiency
topic Nanosheets (NS)
MOSFET
Analog operation
f(T)
Transistor Efficiency
description This work presents an experimental analysis of the trade-off between transistor efficiency (gm/I-D) and unit gain frequency (f(T)) of nanosheet field effect transistors (NSFETs) with different metal gate (MG) stack, considering the influence of high temperature (T), until T=200 degrees C. The results are very promising for both MG stacks. The MG stack (n*) presents a high f(T) about 260 GHz (T=25 degrees C and L=28 nm) and a gm/I-D about 37 V-1 (T=25 degrees C and L=200 nm). The MG stack (m*) also presents very good characteristics, like a f(T) about 252 GHz (T=25 degrees C and L=28 nm) and a gm/In about 35 V-1 (T=25 degrees C and L=200 nm). From the analyses as a function of the inversion coefficient (IC), it was possible to determine that the optimal operation point occurs in the transition from moderate to strong inversion for L=28 nm and it is in strong inversion for long channel devices. In all cases, although the intrinsic voltage gain (Av) is degraded moving away from weak inversion, the degradation was not very pronounced up to the optimal operation point and considering the temperature variation, the Av presents a greater stability at the optimal point than in weak inversion.
publishDate 2021
dc.date.none.fl_str_mv 2021-01-01
2022-11-30T13:38:23Z
2022-11-30T13:38:23Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/conferenceObject
format conferenceObject
status_str publishedVersion
dc.identifier.uri.fl_str_mv http://dx.doi.org/10.1109/EuroSOI-ULIS53016.2021.9560185
2021 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (eurosoi-ulis). New York: Ieee, 4 p., 2021.
2330-5738
http://hdl.handle.net/11449/237553
10.1109/EuroSOI-ULIS53016.2021.9560185
WOS:000790181800015
url http://dx.doi.org/10.1109/EuroSOI-ULIS53016.2021.9560185
http://hdl.handle.net/11449/237553
identifier_str_mv 2021 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (eurosoi-ulis). New York: Ieee, 4 p., 2021.
2330-5738
10.1109/EuroSOI-ULIS53016.2021.9560185
WOS:000790181800015
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv 2021 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (eurosoi-ulis)
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv 4
dc.publisher.none.fl_str_mv Ieee
publisher.none.fl_str_mv Ieee
dc.source.none.fl_str_mv Web of Science
reponame:Repositório Institucional da UNESP
instname:Universidade Estadual Paulista (UNESP)
instacron:UNESP
instname_str Universidade Estadual Paulista (UNESP)
instacron_str UNESP
institution UNESP
reponame_str Repositório Institucional da UNESP
collection Repositório Institucional da UNESP
repository.name.fl_str_mv Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)
repository.mail.fl_str_mv
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