Reversible Circuit Optimization based on Tabu Search
Autor(a) principal: | |
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Data de Publicação: | 2018 |
Outros Autores: | , , |
Tipo de documento: | Artigo de conferência |
Idioma: | eng |
Título da fonte: | Repositório Institucional da UNESP |
Texto Completo: | http://dx.doi.org/10.1109/ISMVL.2018.00026 http://hdl.handle.net/11449/209499 |
Resumo: | An algorithm, based on the meta-heuristic technique known as Tabu Search, was developed to optimize reversible circuits. A set of rules that can modify the reversible circuit to be optimized are applied. The movement of gates may increase, decrease, or leave the number of gates unchanged. In this context, an algorithm was developed to control the application of these rules. The idea of the proposed algorithm is to divide the reversible circuit into neighborhoods and perform a Tabu search to find the best local solution in each neighborhood, penalizing the rules that were already applied in the iteration. The results of optimized benchmark functions shows the efficiency of the algorithm, reducing reversible circuits by up to 62%. |
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Repositório Institucional da UNESP |
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2946 |
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Reversible Circuit Optimization based on Tabu SearchAn algorithm, based on the meta-heuristic technique known as Tabu Search, was developed to optimize reversible circuits. A set of rules that can modify the reversible circuit to be optimized are applied. The movement of gates may increase, decrease, or leave the number of gates unchanged. In this context, an algorithm was developed to control the application of these rules. The idea of the proposed algorithm is to divide the reversible circuit into neighborhoods and perform a Tabu search to find the best local solution in each neighborhood, penalizing the rules that were already applied in the iteration. The results of optimized benchmark functions shows the efficiency of the algorithm, reducing reversible circuits by up to 62%.Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)NSERCFEIS Univ Estadual Paulista, Dept Elect Engn, Ilha Solteira, SP, BrazilUniv New Brunswick, Fac Comp Sci, Fredericton, NB, CanadaFEIS Univ Estadual Paulista, Dept Elect Engn, Ilha Solteira, SP, BrazilCNPq: 309193/2015-0IeeeUniversidade Estadual Paulista (Unesp)Univ New BrunswickAlmeida, Alexandre A. A. de [UNESP]Dueck, Gerhard W.Silva, Alexandre C. R. da [UNESP]IEEE2021-06-25T12:20:24Z2021-06-25T12:20:24Z2018-01-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject103-108http://dx.doi.org/10.1109/ISMVL.2018.000262018 Ieee 48th International Symposium On Multiple-valued Logic (ismvl 2018). New York: Ieee, p. 103-108, 2018.0195-623Xhttp://hdl.handle.net/11449/20949910.1109/ISMVL.2018.00026WOS:000574768400018Web of Sciencereponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPeng2018 Ieee 48th International Symposium On Multiple-valued Logic (ismvl 2018)info:eu-repo/semantics/openAccess2024-07-04T19:11:33Zoai:repositorio.unesp.br:11449/209499Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-08-05T17:00:33.203036Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false |
dc.title.none.fl_str_mv |
Reversible Circuit Optimization based on Tabu Search |
title |
Reversible Circuit Optimization based on Tabu Search |
spellingShingle |
Reversible Circuit Optimization based on Tabu Search Almeida, Alexandre A. A. de [UNESP] |
title_short |
Reversible Circuit Optimization based on Tabu Search |
title_full |
Reversible Circuit Optimization based on Tabu Search |
title_fullStr |
Reversible Circuit Optimization based on Tabu Search |
title_full_unstemmed |
Reversible Circuit Optimization based on Tabu Search |
title_sort |
Reversible Circuit Optimization based on Tabu Search |
author |
Almeida, Alexandre A. A. de [UNESP] |
author_facet |
Almeida, Alexandre A. A. de [UNESP] Dueck, Gerhard W. Silva, Alexandre C. R. da [UNESP] IEEE |
author_role |
author |
author2 |
Dueck, Gerhard W. Silva, Alexandre C. R. da [UNESP] IEEE |
author2_role |
author author author |
dc.contributor.none.fl_str_mv |
Universidade Estadual Paulista (Unesp) Univ New Brunswick |
dc.contributor.author.fl_str_mv |
Almeida, Alexandre A. A. de [UNESP] Dueck, Gerhard W. Silva, Alexandre C. R. da [UNESP] IEEE |
description |
An algorithm, based on the meta-heuristic technique known as Tabu Search, was developed to optimize reversible circuits. A set of rules that can modify the reversible circuit to be optimized are applied. The movement of gates may increase, decrease, or leave the number of gates unchanged. In this context, an algorithm was developed to control the application of these rules. The idea of the proposed algorithm is to divide the reversible circuit into neighborhoods and perform a Tabu search to find the best local solution in each neighborhood, penalizing the rules that were already applied in the iteration. The results of optimized benchmark functions shows the efficiency of the algorithm, reducing reversible circuits by up to 62%. |
publishDate |
2018 |
dc.date.none.fl_str_mv |
2018-01-01 2021-06-25T12:20:24Z 2021-06-25T12:20:24Z |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/conferenceObject |
format |
conferenceObject |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://dx.doi.org/10.1109/ISMVL.2018.00026 2018 Ieee 48th International Symposium On Multiple-valued Logic (ismvl 2018). New York: Ieee, p. 103-108, 2018. 0195-623X http://hdl.handle.net/11449/209499 10.1109/ISMVL.2018.00026 WOS:000574768400018 |
url |
http://dx.doi.org/10.1109/ISMVL.2018.00026 http://hdl.handle.net/11449/209499 |
identifier_str_mv |
2018 Ieee 48th International Symposium On Multiple-valued Logic (ismvl 2018). New York: Ieee, p. 103-108, 2018. 0195-623X 10.1109/ISMVL.2018.00026 WOS:000574768400018 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.none.fl_str_mv |
2018 Ieee 48th International Symposium On Multiple-valued Logic (ismvl 2018) |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.format.none.fl_str_mv |
103-108 |
dc.publisher.none.fl_str_mv |
Ieee |
publisher.none.fl_str_mv |
Ieee |
dc.source.none.fl_str_mv |
Web of Science reponame:Repositório Institucional da UNESP instname:Universidade Estadual Paulista (UNESP) instacron:UNESP |
instname_str |
Universidade Estadual Paulista (UNESP) |
instacron_str |
UNESP |
institution |
UNESP |
reponame_str |
Repositório Institucional da UNESP |
collection |
Repositório Institucional da UNESP |
repository.name.fl_str_mv |
Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP) |
repository.mail.fl_str_mv |
|
_version_ |
1808128738651537408 |