All-digital time-to-digital converter design methodology based on structured data paths
Autor(a) principal: | |
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Data de Publicação: | 2019 |
Outros Autores: | , |
Tipo de documento: | Artigo |
Idioma: | eng |
Título da fonte: | Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
Texto Completo: | http://hdl.handle.net/1822/71336 |
Resumo: | Time-to-Digital Converters (TDC) are popular circuits in many applications, where high resolution time measurements are required, for example, in Positron Emission Tomography (PET). Besides its resolution, the TDC's linearity is also an important performance indicator, therefore calibration circuits usually play an important role on TDCs architectures. This paper presents an all-digital TDC implemented using Structured Datapath to reduce the need for calibration circuitry and cells custom design, without compromising the TDC's linearity. The proposed design is fully implementable using a Hardware Description Language (HDL) and enables a complete design flow automation, reducing both development time and system's complexity. The TDC is based on a Delay Locked Loop (DLL) paired with a coarse counter to increase measurement range. The proposed architecture and the design approach have proven to be efficient in developing a high resolution TDC with high linearity. The proposed TDC was implemented in TSMC 0.18 μm CMOS technology process achieving a resolution of 180ps, with Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) under 0.6 LSB. |
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All-digital time-to-digital converter design methodology based on structured data pathsASICStructured data pathTDCTime-to-digital convertersCiências Naturais::Ciências da Computação e da InformaçãoScience & TechnologyTime-to-Digital Converters (TDC) are popular circuits in many applications, where high resolution time measurements are required, for example, in Positron Emission Tomography (PET). Besides its resolution, the TDC's linearity is also an important performance indicator, therefore calibration circuits usually play an important role on TDCs architectures. This paper presents an all-digital TDC implemented using Structured Datapath to reduce the need for calibration circuitry and cells custom design, without compromising the TDC's linearity. The proposed design is fully implementable using a Hardware Description Language (HDL) and enables a complete design flow automation, reducing both development time and system's complexity. The TDC is based on a Delay Locked Loop (DLL) paired with a coarse counter to increase measurement range. The proposed architecture and the design approach have proven to be efficient in developing a high resolution TDC with high linearity. The proposed TDC was implemented in TSMC 0.18 μm CMOS technology process achieving a resolution of 180ps, with Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) under 0.6 LSB.FRCT - Fundo Regional para a Ciência e Tecnologia(PDE/BDE/114562/2016)Institute of Electrical and Electronics Engineers Inc.Universidade do MinhoMachado, RuiCabral, JorgeAlves, Filipe Manuel Serra2019-082019-08-01T00:00:00Zinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfhttp://hdl.handle.net/1822/71336engMachado, R., Cabral, J., & Alves, F. S. (2019). All-digital time-to-digital converter design methodology based on structured data paths. IEEE Access, 7, 108447-1084572169-353610.1109/ACCESS.2019.2933496https://ieeexplore.ieee.org/abstract/document/8793078info:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2023-07-21T12:22:56Zoai:repositorium.sdum.uminho.pt:1822/71336Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireopendoar:71602024-03-19T19:16:32.461293Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse |
dc.title.none.fl_str_mv |
All-digital time-to-digital converter design methodology based on structured data paths |
title |
All-digital time-to-digital converter design methodology based on structured data paths |
spellingShingle |
All-digital time-to-digital converter design methodology based on structured data paths Machado, Rui ASIC Structured data path TDC Time-to-digital converters Ciências Naturais::Ciências da Computação e da Informação Science & Technology |
title_short |
All-digital time-to-digital converter design methodology based on structured data paths |
title_full |
All-digital time-to-digital converter design methodology based on structured data paths |
title_fullStr |
All-digital time-to-digital converter design methodology based on structured data paths |
title_full_unstemmed |
All-digital time-to-digital converter design methodology based on structured data paths |
title_sort |
All-digital time-to-digital converter design methodology based on structured data paths |
author |
Machado, Rui |
author_facet |
Machado, Rui Cabral, Jorge Alves, Filipe Manuel Serra |
author_role |
author |
author2 |
Cabral, Jorge Alves, Filipe Manuel Serra |
author2_role |
author author |
dc.contributor.none.fl_str_mv |
Universidade do Minho |
dc.contributor.author.fl_str_mv |
Machado, Rui Cabral, Jorge Alves, Filipe Manuel Serra |
dc.subject.por.fl_str_mv |
ASIC Structured data path TDC Time-to-digital converters Ciências Naturais::Ciências da Computação e da Informação Science & Technology |
topic |
ASIC Structured data path TDC Time-to-digital converters Ciências Naturais::Ciências da Computação e da Informação Science & Technology |
description |
Time-to-Digital Converters (TDC) are popular circuits in many applications, where high resolution time measurements are required, for example, in Positron Emission Tomography (PET). Besides its resolution, the TDC's linearity is also an important performance indicator, therefore calibration circuits usually play an important role on TDCs architectures. This paper presents an all-digital TDC implemented using Structured Datapath to reduce the need for calibration circuitry and cells custom design, without compromising the TDC's linearity. The proposed design is fully implementable using a Hardware Description Language (HDL) and enables a complete design flow automation, reducing both development time and system's complexity. The TDC is based on a Delay Locked Loop (DLL) paired with a coarse counter to increase measurement range. The proposed architecture and the design approach have proven to be efficient in developing a high resolution TDC with high linearity. The proposed TDC was implemented in TSMC 0.18 μm CMOS technology process achieving a resolution of 180ps, with Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) under 0.6 LSB. |
publishDate |
2019 |
dc.date.none.fl_str_mv |
2019-08 2019-08-01T00:00:00Z |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/article |
format |
article |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://hdl.handle.net/1822/71336 |
url |
http://hdl.handle.net/1822/71336 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.none.fl_str_mv |
Machado, R., Cabral, J., & Alves, F. S. (2019). All-digital time-to-digital converter design methodology based on structured data paths. IEEE Access, 7, 108447-108457 2169-3536 10.1109/ACCESS.2019.2933496 https://ieeexplore.ieee.org/abstract/document/8793078 |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.format.none.fl_str_mv |
application/pdf |
dc.publisher.none.fl_str_mv |
Institute of Electrical and Electronics Engineers Inc. |
publisher.none.fl_str_mv |
Institute of Electrical and Electronics Engineers Inc. |
dc.source.none.fl_str_mv |
reponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação instacron:RCAAP |
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Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação |
instacron_str |
RCAAP |
institution |
RCAAP |
reponame_str |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
collection |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
repository.name.fl_str_mv |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação |
repository.mail.fl_str_mv |
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1799132614660980736 |