Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias
Autor(a) principal: | |
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Data de Publicação: | 2019 |
Outros Autores: | , , , , , , |
Tipo de documento: | Artigo |
Idioma: | eng |
Título da fonte: | Repositório Institucional da UNESP |
Texto Completo: | http://dx.doi.org/10.1088/1361-6641/aafccc http://hdl.handle.net/11449/187541 |
Resumo: | This paper presents a comparison between nMOS and pMOS Ω-Gate Nanowire for different channel width (W NW ) down to 10 nm as a function of the large back gate bias variation (from +20 to -20 V) experimentally and by simulation. The main digital and analog parameters are analyzed in these devices as threshold voltage, subthreshold swing (SS), transconductance, transistor efficiency, Early Voltage and intrinsic voltage gain for transistor channel width from 220 nm down to 10 nm. It is shown that narrow channel devices (W NW = 10 nm) present a small variation on the analyzed parameters as a function of back gate voltage due to stronger electrostatic control between gate and channel considering that they are effectively working like a gate-all-around devices. In general, all the nMOS parameters presents better results compared to pMOS due to the mobility enhancements. For wider devices (W NW = 220 nm), it depends on the back interface condition. For a large enough back gate bias that tends to create a back interface conduction (+20 V for nMOS and -20 V for pMOS), the SS degrades from 61 mV dec -1 (W NW = 10 nm) to 68 mV dec -1 (W NW = 220 nm). However for a large enough back gate bias that induces a non-conduction region (tends to accumulation) at back interface (-20 V for nMOS and +20 V for pMOS) the SS changes from 60 to 62 mV dec -1 at the same W NW range, which is a very acceptable results. Additionally, the drain current (I ON ) and transconductance (linear and saturation regions) increase for this back gate bias condition (tends to accumulation), working almost like a pseudo nanosheet device for these parameters, avoiding also the parasitic conduction at the back interface. However, in spite of the intrinsic voltage gain is almost independent of the back gate bias, it improves of at least 10 dB for narrow devices due to the higher Early voltage and almost similar transistor efficiency than the wider ones. |
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Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate biasanalog parametersnanowireomega-gateSOIThis paper presents a comparison between nMOS and pMOS Ω-Gate Nanowire for different channel width (W NW ) down to 10 nm as a function of the large back gate bias variation (from +20 to -20 V) experimentally and by simulation. The main digital and analog parameters are analyzed in these devices as threshold voltage, subthreshold swing (SS), transconductance, transistor efficiency, Early Voltage and intrinsic voltage gain for transistor channel width from 220 nm down to 10 nm. It is shown that narrow channel devices (W NW = 10 nm) present a small variation on the analyzed parameters as a function of back gate voltage due to stronger electrostatic control between gate and channel considering that they are effectively working like a gate-all-around devices. In general, all the nMOS parameters presents better results compared to pMOS due to the mobility enhancements. For wider devices (W NW = 220 nm), it depends on the back interface condition. For a large enough back gate bias that tends to create a back interface conduction (+20 V for nMOS and -20 V for pMOS), the SS degrades from 61 mV dec -1 (W NW = 10 nm) to 68 mV dec -1 (W NW = 220 nm). However for a large enough back gate bias that induces a non-conduction region (tends to accumulation) at back interface (-20 V for nMOS and +20 V for pMOS) the SS changes from 60 to 62 mV dec -1 at the same W NW range, which is a very acceptable results. Additionally, the drain current (I ON ) and transconductance (linear and saturation regions) increase for this back gate bias condition (tends to accumulation), working almost like a pseudo nanosheet device for these parameters, avoiding also the parasitic conduction at the back interface. However, in spite of the intrinsic voltage gain is almost independent of the back gate bias, it improves of at least 10 dB for narrow devices due to the higher Early voltage and almost similar transistor efficiency than the wider ones.LSI/PSI/USP University of Sao PauloFaculdade de Tecnologia de Sao Paulo e Faculdade de Tecnologia de Osasco CEETEPSSao Paulo State University (UNESP) Sao Joao da Boa VistaCEA LETI, Minatec Campus and University Grenoble AlpesSao Paulo State University (UNESP) Sao Joao da Boa VistaUniversidade de São Paulo (USP)CEETEPSUniversidade Estadual Paulista (Unesp)LETIItocazu, V. T.Almeida, L. M.Sonnenberg, V.Agopian, P. G.D. [UNESP]Barraud, S.Vinet, M.Faynot, O.Martino, J. A.2019-10-06T15:39:25Z2019-10-06T15:39:25Z2019-01-30info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articlehttp://dx.doi.org/10.1088/1361-6641/aafcccSemiconductor Science and Technology, v. 34, n. 3, 2019.1361-66410268-1242http://hdl.handle.net/11449/18754110.1088/1361-6641/aafccc2-s2.0-8506409228704969095954656960000-0002-0886-7798Scopusreponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPengSemiconductor Science and Technologyinfo:eu-repo/semantics/openAccess2021-10-23T20:19:26Zoai:repositorio.unesp.br:11449/187541Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462021-10-23T20:19:26Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false |
dc.title.none.fl_str_mv |
Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias |
title |
Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias |
spellingShingle |
Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias Itocazu, V. T. analog parameters nanowire omega-gate SOI |
title_short |
Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias |
title_full |
Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias |
title_fullStr |
Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias |
title_full_unstemmed |
Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias |
title_sort |
Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias |
author |
Itocazu, V. T. |
author_facet |
Itocazu, V. T. Almeida, L. M. Sonnenberg, V. Agopian, P. G.D. [UNESP] Barraud, S. Vinet, M. Faynot, O. Martino, J. A. |
author_role |
author |
author2 |
Almeida, L. M. Sonnenberg, V. Agopian, P. G.D. [UNESP] Barraud, S. Vinet, M. Faynot, O. Martino, J. A. |
author2_role |
author author author author author author author |
dc.contributor.none.fl_str_mv |
Universidade de São Paulo (USP) CEETEPS Universidade Estadual Paulista (Unesp) LETI |
dc.contributor.author.fl_str_mv |
Itocazu, V. T. Almeida, L. M. Sonnenberg, V. Agopian, P. G.D. [UNESP] Barraud, S. Vinet, M. Faynot, O. Martino, J. A. |
dc.subject.por.fl_str_mv |
analog parameters nanowire omega-gate SOI |
topic |
analog parameters nanowire omega-gate SOI |
description |
This paper presents a comparison between nMOS and pMOS Ω-Gate Nanowire for different channel width (W NW ) down to 10 nm as a function of the large back gate bias variation (from +20 to -20 V) experimentally and by simulation. The main digital and analog parameters are analyzed in these devices as threshold voltage, subthreshold swing (SS), transconductance, transistor efficiency, Early Voltage and intrinsic voltage gain for transistor channel width from 220 nm down to 10 nm. It is shown that narrow channel devices (W NW = 10 nm) present a small variation on the analyzed parameters as a function of back gate voltage due to stronger electrostatic control between gate and channel considering that they are effectively working like a gate-all-around devices. In general, all the nMOS parameters presents better results compared to pMOS due to the mobility enhancements. For wider devices (W NW = 220 nm), it depends on the back interface condition. For a large enough back gate bias that tends to create a back interface conduction (+20 V for nMOS and -20 V for pMOS), the SS degrades from 61 mV dec -1 (W NW = 10 nm) to 68 mV dec -1 (W NW = 220 nm). However for a large enough back gate bias that induces a non-conduction region (tends to accumulation) at back interface (-20 V for nMOS and +20 V for pMOS) the SS changes from 60 to 62 mV dec -1 at the same W NW range, which is a very acceptable results. Additionally, the drain current (I ON ) and transconductance (linear and saturation regions) increase for this back gate bias condition (tends to accumulation), working almost like a pseudo nanosheet device for these parameters, avoiding also the parasitic conduction at the back interface. However, in spite of the intrinsic voltage gain is almost independent of the back gate bias, it improves of at least 10 dB for narrow devices due to the higher Early voltage and almost similar transistor efficiency than the wider ones. |
publishDate |
2019 |
dc.date.none.fl_str_mv |
2019-10-06T15:39:25Z 2019-10-06T15:39:25Z 2019-01-30 |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/article |
format |
article |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://dx.doi.org/10.1088/1361-6641/aafccc Semiconductor Science and Technology, v. 34, n. 3, 2019. 1361-6641 0268-1242 http://hdl.handle.net/11449/187541 10.1088/1361-6641/aafccc 2-s2.0-85064092287 0496909595465696 0000-0002-0886-7798 |
url |
http://dx.doi.org/10.1088/1361-6641/aafccc http://hdl.handle.net/11449/187541 |
identifier_str_mv |
Semiconductor Science and Technology, v. 34, n. 3, 2019. 1361-6641 0268-1242 10.1088/1361-6641/aafccc 2-s2.0-85064092287 0496909595465696 0000-0002-0886-7798 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.none.fl_str_mv |
Semiconductor Science and Technology |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.source.none.fl_str_mv |
Scopus reponame:Repositório Institucional da UNESP instname:Universidade Estadual Paulista (UNESP) instacron:UNESP |
instname_str |
Universidade Estadual Paulista (UNESP) |
instacron_str |
UNESP |
institution |
UNESP |
reponame_str |
Repositório Institucional da UNESP |
collection |
Repositório Institucional da UNESP |
repository.name.fl_str_mv |
Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP) |
repository.mail.fl_str_mv |
|
_version_ |
1797789599328632832 |