Analysis of omega-gate nanowire soi mosfet under analog point of view

Detalhes bibliográficos
Autor(a) principal: Perina, Welder F.
Data de Publicação: 2020
Outros Autores: Martino, João A., Agopian, Paula G. D. [UNESP]
Tipo de documento: Artigo
Idioma: eng
Título da fonte: Repositório Institucional da UNESP
Texto Completo: http://dx.doi.org/10.29292/jics.v15i1.113
http://hdl.handle.net/11449/198960
Resumo: This paper presents an evaluation of omega-gate nanowire n-and p-type SOI MOSFETs performance focusing on the main analog figures of merit, like saturation transcon-ductance (gmsat), output conductance (gD), transconductance over drain current (gm/IDS) ratio, Early voltage (VEA), intrinsic gain (AV) and unit gain frequency (ft). The different channel widths (WNW) and channel lengths (L) were also evaluated. These devices presented values of subthreshold slope near the theoretical limit at room temperature (60 mV/dec), and in the worst case, a DIBL value smaller than 70 mV/V. Showing its immunity to short channel effects (SCEs) in the studied channel length range. The narrowest device showed great electrostatic coupling, improving gm, presenting an unit gain frequency over 200 GHz and intrinsic voltage gain over 80 dB. These values suggests that this device is capable of achieving good performance on new applications such as 5G communications and In-ternet-of-Things (IoT).
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spelling Analysis of omega-gate nanowire soi mosfet under analog point of viewIntrinsic Voltage GainNanowireOmega-gateSOI MOSFETUnit-gain FrequencyThis paper presents an evaluation of omega-gate nanowire n-and p-type SOI MOSFETs performance focusing on the main analog figures of merit, like saturation transcon-ductance (gmsat), output conductance (gD), transconductance over drain current (gm/IDS) ratio, Early voltage (VEA), intrinsic gain (AV) and unit gain frequency (ft). The different channel widths (WNW) and channel lengths (L) were also evaluated. These devices presented values of subthreshold slope near the theoretical limit at room temperature (60 mV/dec), and in the worst case, a DIBL value smaller than 70 mV/V. Showing its immunity to short channel effects (SCEs) in the studied channel length range. The narrowest device showed great electrostatic coupling, improving gm, presenting an unit gain frequency over 200 GHz and intrinsic voltage gain over 80 dB. These values suggests that this device is capable of achieving good performance on new applications such as 5G communications and In-ternet-of-Things (IoT).Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)LSI/PSI/USP University of São PauloUNESP São Paulo State UniversityUNESP São Paulo State UniversityUniversidade de São Paulo (USP)Universidade Estadual Paulista (Unesp)Perina, Welder F.Martino, João A.Agopian, Paula G. D. [UNESP]2020-12-12T01:26:49Z2020-12-12T01:26:49Z2020-01-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articlehttp://dx.doi.org/10.29292/jics.v15i1.113Journal of Integrated Circuits and Systems, v. 15, n. 1, 2020.1872-02341807-1953http://hdl.handle.net/11449/19896010.29292/jics.v15i1.1132-s2.0-85086123912Scopusreponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPengJournal of Integrated Circuits and Systemsinfo:eu-repo/semantics/openAccess2021-10-22T21:15:52Zoai:repositorio.unesp.br:11449/198960Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462021-10-22T21:15:52Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false
dc.title.none.fl_str_mv Analysis of omega-gate nanowire soi mosfet under analog point of view
title Analysis of omega-gate nanowire soi mosfet under analog point of view
spellingShingle Analysis of omega-gate nanowire soi mosfet under analog point of view
Perina, Welder F.
Intrinsic Voltage Gain
Nanowire
Omega-gate
SOI MOSFET
Unit-gain Frequency
title_short Analysis of omega-gate nanowire soi mosfet under analog point of view
title_full Analysis of omega-gate nanowire soi mosfet under analog point of view
title_fullStr Analysis of omega-gate nanowire soi mosfet under analog point of view
title_full_unstemmed Analysis of omega-gate nanowire soi mosfet under analog point of view
title_sort Analysis of omega-gate nanowire soi mosfet under analog point of view
author Perina, Welder F.
author_facet Perina, Welder F.
Martino, João A.
Agopian, Paula G. D. [UNESP]
author_role author
author2 Martino, João A.
Agopian, Paula G. D. [UNESP]
author2_role author
author
dc.contributor.none.fl_str_mv Universidade de São Paulo (USP)
Universidade Estadual Paulista (Unesp)
dc.contributor.author.fl_str_mv Perina, Welder F.
Martino, João A.
Agopian, Paula G. D. [UNESP]
dc.subject.por.fl_str_mv Intrinsic Voltage Gain
Nanowire
Omega-gate
SOI MOSFET
Unit-gain Frequency
topic Intrinsic Voltage Gain
Nanowire
Omega-gate
SOI MOSFET
Unit-gain Frequency
description This paper presents an evaluation of omega-gate nanowire n-and p-type SOI MOSFETs performance focusing on the main analog figures of merit, like saturation transcon-ductance (gmsat), output conductance (gD), transconductance over drain current (gm/IDS) ratio, Early voltage (VEA), intrinsic gain (AV) and unit gain frequency (ft). The different channel widths (WNW) and channel lengths (L) were also evaluated. These devices presented values of subthreshold slope near the theoretical limit at room temperature (60 mV/dec), and in the worst case, a DIBL value smaller than 70 mV/V. Showing its immunity to short channel effects (SCEs) in the studied channel length range. The narrowest device showed great electrostatic coupling, improving gm, presenting an unit gain frequency over 200 GHz and intrinsic voltage gain over 80 dB. These values suggests that this device is capable of achieving good performance on new applications such as 5G communications and In-ternet-of-Things (IoT).
publishDate 2020
dc.date.none.fl_str_mv 2020-12-12T01:26:49Z
2020-12-12T01:26:49Z
2020-01-01
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/article
format article
status_str publishedVersion
dc.identifier.uri.fl_str_mv http://dx.doi.org/10.29292/jics.v15i1.113
Journal of Integrated Circuits and Systems, v. 15, n. 1, 2020.
1872-0234
1807-1953
http://hdl.handle.net/11449/198960
10.29292/jics.v15i1.113
2-s2.0-85086123912
url http://dx.doi.org/10.29292/jics.v15i1.113
http://hdl.handle.net/11449/198960
identifier_str_mv Journal of Integrated Circuits and Systems, v. 15, n. 1, 2020.
1872-0234
1807-1953
10.29292/jics.v15i1.113
2-s2.0-85086123912
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv Journal of Integrated Circuits and Systems
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.source.none.fl_str_mv Scopus
reponame:Repositório Institucional da UNESP
instname:Universidade Estadual Paulista (UNESP)
instacron:UNESP
instname_str Universidade Estadual Paulista (UNESP)
instacron_str UNESP
institution UNESP
reponame_str Repositório Institucional da UNESP
collection Repositório Institucional da UNESP
repository.name.fl_str_mv Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)
repository.mail.fl_str_mv
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