Back Gate Influence on Transistor Efficiency of SOI nMOS Omega-gate Nanowire down to 10nm Width
Autor(a) principal: | |
---|---|
Data de Publicação: | 2017 |
Outros Autores: | , , , , , , , |
Tipo de documento: | Artigo de conferência |
Idioma: | eng |
Título da fonte: | Repositório Institucional da UNESP |
Texto Completo: | http://hdl.handle.net/11449/160133 |
Resumo: | This paper shows the influence of back gate bias on transistor efficiency of nMOS SOI Omega-gate nanowire, for different width and channel length. Threshold voltage and subthreshold swing present a higher variation with the back gate bias variation in wider devices. Long channel devices present better efficiency due to the better subthreshold swing, the same reason for the narrow devices have a better efficiency. Wider devices have a higher variation in efficiency when the back gate is biased. The transistor efficiency increases when the back gate is negative biased due to the better electrostatic coupling between gate and channel. |
id |
UNSP_d989baef10bd9e23718cc19c1addfe98 |
---|---|
oai_identifier_str |
oai:repositorio.unesp.br:11449/160133 |
network_acronym_str |
UNSP |
network_name_str |
Repositório Institucional da UNESP |
repository_id_str |
2946 |
spelling |
Back Gate Influence on Transistor Efficiency of SOI nMOS Omega-gate Nanowire down to 10nm WidthSOIOmega-GateNanowireBack gateTransistor EfficiencyThis paper shows the influence of back gate bias on transistor efficiency of nMOS SOI Omega-gate nanowire, for different width and channel length. Threshold voltage and subthreshold swing present a higher variation with the back gate bias variation in wider devices. Long channel devices present better efficiency due to the better subthreshold swing, the same reason for the narrow devices have a better efficiency. Wider devices have a higher variation in efficiency when the back gate is biased. The transistor efficiency increases when the back gate is negative biased due to the better electrostatic coupling between gate and channel.Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)Univ Sao Paulo, LSI PSI USP, Sao Paulo, BrazilFATEC SP, Sao Paulo, BrazilFATEC OSASCO CEETEPS, Sao Paulo, BrazilSao Paulo State Univ UNESP, Sao Joao Da Boa Vista, BrazilCEA, LETI, Minatec Campus, F-38054 Grenoble, FranceUniv Grenoble Alpes, F-38054 Grenoble, FranceSao Paulo State Univ UNESP, Sao Joao Da Boa Vista, BrazilIeeeUniversidade de São Paulo (USP)FATEC SPFATEC OSASCO CEETEPSUniversidade Estadual Paulista (Unesp)CEAUniv Grenoble AlpesItocazu, Vitor T.Luciano, M. AlmeidaSonnenberg, VictorAgopian, Paula G. D. [UNESP]Barraud, SylvainVinet, MaudFaynot, OlivierMartino, Joao A.IEEE2018-11-26T15:47:36Z2018-11-26T15:47:36Z2017-01-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject42017 32nd Symposium On Microelectronics Technology And Devices (sbmicro): Chip On The Sands. New York: Ieee, 4 p., 2017.http://hdl.handle.net/11449/160133WOS:00042652450005204969095954656960000-0002-0886-7798Web of Sciencereponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPeng2017 32nd Symposium On Microelectronics Technology And Devices (sbmicro): Chip On The Sandsinfo:eu-repo/semantics/openAccess2021-10-23T21:47:07Zoai:repositorio.unesp.br:11449/160133Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462021-10-23T21:47:07Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false |
dc.title.none.fl_str_mv |
Back Gate Influence on Transistor Efficiency of SOI nMOS Omega-gate Nanowire down to 10nm Width |
title |
Back Gate Influence on Transistor Efficiency of SOI nMOS Omega-gate Nanowire down to 10nm Width |
spellingShingle |
Back Gate Influence on Transistor Efficiency of SOI nMOS Omega-gate Nanowire down to 10nm Width Itocazu, Vitor T. SOI Omega-Gate Nanowire Back gate Transistor Efficiency |
title_short |
Back Gate Influence on Transistor Efficiency of SOI nMOS Omega-gate Nanowire down to 10nm Width |
title_full |
Back Gate Influence on Transistor Efficiency of SOI nMOS Omega-gate Nanowire down to 10nm Width |
title_fullStr |
Back Gate Influence on Transistor Efficiency of SOI nMOS Omega-gate Nanowire down to 10nm Width |
title_full_unstemmed |
Back Gate Influence on Transistor Efficiency of SOI nMOS Omega-gate Nanowire down to 10nm Width |
title_sort |
Back Gate Influence on Transistor Efficiency of SOI nMOS Omega-gate Nanowire down to 10nm Width |
author |
Itocazu, Vitor T. |
author_facet |
Itocazu, Vitor T. Luciano, M. Almeida Sonnenberg, Victor Agopian, Paula G. D. [UNESP] Barraud, Sylvain Vinet, Maud Faynot, Olivier Martino, Joao A. IEEE |
author_role |
author |
author2 |
Luciano, M. Almeida Sonnenberg, Victor Agopian, Paula G. D. [UNESP] Barraud, Sylvain Vinet, Maud Faynot, Olivier Martino, Joao A. IEEE |
author2_role |
author author author author author author author author |
dc.contributor.none.fl_str_mv |
Universidade de São Paulo (USP) FATEC SP FATEC OSASCO CEETEPS Universidade Estadual Paulista (Unesp) CEA Univ Grenoble Alpes |
dc.contributor.author.fl_str_mv |
Itocazu, Vitor T. Luciano, M. Almeida Sonnenberg, Victor Agopian, Paula G. D. [UNESP] Barraud, Sylvain Vinet, Maud Faynot, Olivier Martino, Joao A. IEEE |
dc.subject.por.fl_str_mv |
SOI Omega-Gate Nanowire Back gate Transistor Efficiency |
topic |
SOI Omega-Gate Nanowire Back gate Transistor Efficiency |
description |
This paper shows the influence of back gate bias on transistor efficiency of nMOS SOI Omega-gate nanowire, for different width and channel length. Threshold voltage and subthreshold swing present a higher variation with the back gate bias variation in wider devices. Long channel devices present better efficiency due to the better subthreshold swing, the same reason for the narrow devices have a better efficiency. Wider devices have a higher variation in efficiency when the back gate is biased. The transistor efficiency increases when the back gate is negative biased due to the better electrostatic coupling between gate and channel. |
publishDate |
2017 |
dc.date.none.fl_str_mv |
2017-01-01 2018-11-26T15:47:36Z 2018-11-26T15:47:36Z |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/conferenceObject |
format |
conferenceObject |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
2017 32nd Symposium On Microelectronics Technology And Devices (sbmicro): Chip On The Sands. New York: Ieee, 4 p., 2017. http://hdl.handle.net/11449/160133 WOS:000426524500052 0496909595465696 0000-0002-0886-7798 |
identifier_str_mv |
2017 32nd Symposium On Microelectronics Technology And Devices (sbmicro): Chip On The Sands. New York: Ieee, 4 p., 2017. WOS:000426524500052 0496909595465696 0000-0002-0886-7798 |
url |
http://hdl.handle.net/11449/160133 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.none.fl_str_mv |
2017 32nd Symposium On Microelectronics Technology And Devices (sbmicro): Chip On The Sands |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.format.none.fl_str_mv |
4 |
dc.publisher.none.fl_str_mv |
Ieee |
publisher.none.fl_str_mv |
Ieee |
dc.source.none.fl_str_mv |
Web of Science reponame:Repositório Institucional da UNESP instname:Universidade Estadual Paulista (UNESP) instacron:UNESP |
instname_str |
Universidade Estadual Paulista (UNESP) |
instacron_str |
UNESP |
institution |
UNESP |
reponame_str |
Repositório Institucional da UNESP |
collection |
Repositório Institucional da UNESP |
repository.name.fl_str_mv |
Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP) |
repository.mail.fl_str_mv |
|
_version_ |
1799964508852060160 |