Thread-Level Speculation on Hardware Transactional Memory Architectures

Detalhes bibliográficos
Autor(a) principal: JUAN JESUS SALAMANCA GUILLEN
Data de Publicação: 2016
Tipo de documento: Tese
Título da fonte: Portal de Dados Abertos da CAPES
Texto Completo: https://sucupira.capes.gov.br/sucupira/public/consultas/coleta/trabalhoConclusao/viewTrabalhoConclusao.jsf?popup=true&id_trabalho=4013331
id BRCRIS_63d93627d7b2d994e126070a48331a7f
network_acronym_str CAPES
network_name_str Portal de Dados Abertos da CAPES
dc.title.pt-BR.fl_str_mv Thread-Level Speculation on Hardware Transactional Memory Architectures
title Thread-Level Speculation on Hardware Transactional Memory Architectures
spellingShingle Thread-Level Speculation on Hardware Transactional Memory Architectures
Transactional Memory
JUAN JESUS SALAMANCA GUILLEN
title_short Thread-Level Speculation on Hardware Transactional Memory Architectures
title_full Thread-Level Speculation on Hardware Transactional Memory Architectures
title_fullStr Thread-Level Speculation on Hardware Transactional Memory Architectures
Thread-Level Speculation on Hardware Transactional Memory Architectures
title_full_unstemmed Thread-Level Speculation on Hardware Transactional Memory Architectures
Thread-Level Speculation on Hardware Transactional Memory Architectures
title_sort Thread-Level Speculation on Hardware Transactional Memory Architectures
topic Transactional Memory
publishDate 2016
format doctoralThesis
url https://sucupira.capes.gov.br/sucupira/public/consultas/coleta/trabalhoConclusao/viewTrabalhoConclusao.jsf?popup=true&id_trabalho=4013331
author_role author
author JUAN JESUS SALAMANCA GUILLEN
author_facet JUAN JESUS SALAMANCA GUILLEN
dc.contributor.authorLattes.fl_str_mv http://lattes.cnpq.br/3496760245467665
dc.identifier.orcid.none.fl_str_mv https://orcid.org/0000-0002-0569-2806
dc.contributor.advisor1.fl_str_mv GUIDO COSTA SOUZA DE ARAUJO
dc.contributor.advisor1Lattes.fl_str_mv http://lattes.cnpq.br/8683914780987242
dc.publisher.none.fl_str_mv UNIVERSIDADE ESTADUAL DE CAMPINAS
publisher.none.fl_str_mv UNIVERSIDADE ESTADUAL DE CAMPINAS
instname_str UNIVERSIDADE ESTADUAL DE CAMPINAS
dc.publisher.program.fl_str_mv CIÊNCIA DA COMPUTAÇÃO
dc.description.course.none.fl_txt_mv CIÊNCIA DA COMPUTAÇÃO
reponame_str Portal de Dados Abertos da CAPES
collection Portal de Dados Abertos da CAPES
spelling CAPESPortal de Dados Abertos da CAPESThread-Level Speculation on Hardware Transactional Memory ArchitecturesThread-Level Speculation on Hardware Transactional Memory ArchitecturesThread-Level Speculation on Hardware Transactional Memory ArchitecturesThread-Level Speculation on Hardware Transactional Memory ArchitecturesThread-Level Speculation on Hardware Transactional Memory ArchitecturesThread-Level Speculation on Hardware Transactional Memory ArchitecturesThread-Level Speculation on Hardware Transactional Memory ArchitecturesTransactional Memory2016doctoralThesishttps://sucupira.capes.gov.br/sucupira/public/consultas/coleta/trabalhoConclusao/viewTrabalhoConclusao.jsf?popup=true&id_trabalho=4013331authorJUAN JESUS SALAMANCA GUILLENhttp://lattes.cnpq.br/3496760245467665https://orcid.org/0000-0002-0569-2806GUIDO COSTA SOUZA DE ARAUJOhttp://lattes.cnpq.br/8683914780987242UNIVERSIDADE ESTADUAL DE CAMPINASUNIVERSIDADE ESTADUAL DE CAMPINASUNIVERSIDADE ESTADUAL DE CAMPINASCIÊNCIA DA COMPUTAÇÃOCIÊNCIA DA COMPUTAÇÃOPortal de Dados Abertos da CAPESPortal de Dados Abertos da CAPES
identifier_str_mv GUILLEN, JUAN JESUS SALAMANCA. Thread-Level Speculation on Hardware Transactional Memory Architectures. 2016. Tese.
dc.identifier.citation.fl_str_mv GUILLEN, JUAN JESUS SALAMANCA. Thread-Level Speculation on Hardware Transactional Memory Architectures. 2016. Tese.
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