MCML Gate Design Methodology and the tradeoffs between MCML and CMOS applications

Detalhes bibliográficos
Autor(a) principal: Bruno Canal
Data de Publicação: 2016
Tipo de documento: Dissertação
Título da fonte: Portal de Dados Abertos da CAPES
Texto Completo: https://sucupira.capes.gov.br/sucupira/public/consultas/coleta/trabalhoConclusao/viewTrabalhoConclusao.jsf?popup=true&id_trabalho=3612496
id BRCRIS_6dcb3774f6eac9f29c07033235c48176
network_acronym_str CAPES
network_name_str Portal de Dados Abertos da CAPES
dc.title.pt-BR.fl_str_mv MCML Gate Design Methodology and the tradeoffs between MCML and CMOS applications
title MCML Gate Design Methodology and the tradeoffs between MCML and CMOS applications
spellingShingle MCML Gate Design Methodology and the tradeoffs between MCML and CMOS applications
Aplicações MCML
MCML Application.
Bruno Canal
title_short MCML Gate Design Methodology and the tradeoffs between MCML and CMOS applications
title_full MCML Gate Design Methodology and the tradeoffs between MCML and CMOS applications
title_fullStr MCML Gate Design Methodology and the tradeoffs between MCML and CMOS applications
MCML Gate Design Methodology and the tradeoffs between MCML and CMOS applications
title_full_unstemmed MCML Gate Design Methodology and the tradeoffs between MCML and CMOS applications
MCML Gate Design Methodology and the tradeoffs between MCML and CMOS applications
title_sort MCML Gate Design Methodology and the tradeoffs between MCML and CMOS applications
topic Aplicações MCML
MCML Application.
publishDate 2016
format masterThesis
url https://sucupira.capes.gov.br/sucupira/public/consultas/coleta/trabalhoConclusao/viewTrabalhoConclusao.jsf?popup=true&id_trabalho=3612496
author_role author
author Bruno Canal
author_facet Bruno Canal
dc.contributor.authorLattes.fl_str_mv http://lattes.cnpq.br/2893820458641169
dc.contributor.advisor1.fl_str_mv Eric Ericson Fabris
dc.contributor.advisor1Lattes.fl_str_mv http://lattes.cnpq.br/3914999081096826
dc.publisher.none.fl_str_mv UNIVERSIDADE FEDERAL DO RIO GRANDE DO SUL
publisher.none.fl_str_mv UNIVERSIDADE FEDERAL DO RIO GRANDE DO SUL
instname_str UNIVERSIDADE FEDERAL DO RIO GRANDE DO SUL
dc.publisher.program.fl_str_mv MICROELETRÔNICA
dc.description.course.none.fl_txt_mv MICROELETRÔNICA
reponame_str Portal de Dados Abertos da CAPES
collection Portal de Dados Abertos da CAPES
spelling CAPESPortal de Dados Abertos da CAPESMCML Gate Design Methodology and the tradeoffs between MCML and CMOS applicationsMCML Gate Design Methodology and the tradeoffs between MCML and CMOS applicationsMCML Gate Design Methodology and the tradeoffs between MCML and CMOS applicationsMCML Gate Design Methodology and the tradeoffs between MCML and CMOS applicationsMCML Gate Design Methodology and the tradeoffs between MCML and CMOS applicationsMCML Gate Design Methodology and the tradeoffs between MCML and CMOS applicationsMCML Gate Design Methodology and the tradeoffs between MCML and CMOS applicationsAplicações MCML2016masterThesishttps://sucupira.capes.gov.br/sucupira/public/consultas/coleta/trabalhoConclusao/viewTrabalhoConclusao.jsf?popup=true&id_trabalho=3612496authorBruno Canalhttp://lattes.cnpq.br/2893820458641169Eric Ericson Fabrishttp://lattes.cnpq.br/3914999081096826UNIVERSIDADE FEDERAL DO RIO GRANDE DO SULUNIVERSIDADE FEDERAL DO RIO GRANDE DO SULUNIVERSIDADE FEDERAL DO RIO GRANDE DO SULMICROELETRÔNICAMICROELETRÔNICAPortal de Dados Abertos da CAPESPortal de Dados Abertos da CAPES
identifier_str_mv Canal, Bruno. MCML Gate Design Methodology and the tradeoffs between MCML and CMOS applications. 2016. Tese.
dc.identifier.citation.fl_str_mv Canal, Bruno. MCML Gate Design Methodology and the tradeoffs between MCML and CMOS applications. 2016. Tese.
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