UTBB MOSFETs Thermal Coupling Analysis in Technological Node Level
Autor(a) principal: | |
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Data de Publicação: | 2020 |
Outros Autores: | , |
Tipo de documento: | Artigo |
Título da fonte: | Biblioteca Digital de Teses e Dissertações da FEI |
Texto Completo: | https://repositorio.fei.edu.br/handle/FEI/3479 |
Resumo: | The main goal of this work is to perform a first-time analysis of the thermal cross-coupling in a system composed by some devices in an integration node degree composed by advanced UTBB SOI MOSFETs through numerical simulations, validated with experimental data from the literature. In this analysis, it could be observed that devices located on the channel length direction provoke a reduced thermal coupling and devices with their drain region next to each other suffer of an increased thermal coupling due to the lumped thermal energy. It also could be observed a degradation in some electrical parameters and in the thermal properties of a device under the influence of surrounded devices biased. |
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Open Journal Systems "Este é um artigo publicado em acesso aberto sob uma licença de código aberto (GPL v2). Fonte: https://jics.org.br/ojs/index.php/JICS/article/view/194. Acesso em 25 nov. 2021.info:eu-repo/semantics/openAccessCOSTA, F. J.DORIA, R. T.Rodrigo Trevisoli Doria2021-11-25T22:33:31Z2021-11-25T22:33:31Z2020-07-31COSTA, F. J.; TREVISOLI, R.; DORIA, R. T.. UTBB MOSFETs Thermal Coupling Analysis in Technological Node Level. JICS. JOURNAL OF INTEGRATED CIRCUITS AND SYSTEMS (ED. PORTUGUÊS), v. 15, n. 2, p. 1-5, 2020.1807-1953https://repositorio.fei.edu.br/handle/FEI/347910.29292/jics.v15i2.194The main goal of this work is to perform a first-time analysis of the thermal cross-coupling in a system composed by some devices in an integration node degree composed by advanced UTBB SOI MOSFETs through numerical simulations, validated with experimental data from the literature. In this analysis, it could be observed that devices located on the channel length direction provoke a reduced thermal coupling and devices with their drain region next to each other suffer of an increased thermal coupling due to the lumped thermal energy. It also could be observed a degradation in some electrical parameters and in the thermal properties of a device under the influence of surrounded devices biased.15215JICS. JOURNAL OF INTEGRATED CIRCUITS AND SYSTEMS (ED. PORTUGUÊS)SOIUTBBSelf-HeatingThermal ResistanceThermal-CouplingUTBB MOSFETs Thermal Coupling Analysis in Technological Node Levelinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articlereponame:Biblioteca Digital de Teses e Dissertações da FEIinstname:Centro Universitário da Fundação Educacional Inaciana (FEI)instacron:FEIhttps://jics.org.br/ojs/index.php/JICS/article/view/194ORIGINALDoria_pddfDoria_pddfapplication/pdf343382https://repositorio.fei.edu.br/bitstream/FEI/3479/1/Doria_pddf3d70fd72abaa261b763ab347f7bc38f1MD51TEXTDoria_pddf.txtDoria_pddf.txtExtracted texttext/plain26457https://repositorio.fei.edu.br/bitstream/FEI/3479/2/Doria_pddf.txtae9785a65a36468a52882dfbf1cbac3dMD52THUMBNAILDoria_pddf.jpgDoria_pddf.jpgGenerated Thumbnailimage/jpeg1750https://repositorio.fei.edu.br/bitstream/FEI/3479/3/Doria_pddf.jpgf76591b0362febbb182f652c44369644MD53FEI/34792021-11-26 04:00:30.89Biblioteca Digital de Teses e Dissertaçõeshttp://sofia.fei.edu.br/pergamum/biblioteca/PRI |
dc.title.pt_BR.fl_str_mv |
UTBB MOSFETs Thermal Coupling Analysis in Technological Node Level |
title |
UTBB MOSFETs Thermal Coupling Analysis in Technological Node Level |
spellingShingle |
UTBB MOSFETs Thermal Coupling Analysis in Technological Node Level COSTA, F. J. SOI UTBB Self-Heating Thermal Resistance Thermal-Coupling |
title_short |
UTBB MOSFETs Thermal Coupling Analysis in Technological Node Level |
title_full |
UTBB MOSFETs Thermal Coupling Analysis in Technological Node Level |
title_fullStr |
UTBB MOSFETs Thermal Coupling Analysis in Technological Node Level |
title_full_unstemmed |
UTBB MOSFETs Thermal Coupling Analysis in Technological Node Level |
title_sort |
UTBB MOSFETs Thermal Coupling Analysis in Technological Node Level |
author |
COSTA, F. J. |
author_facet |
COSTA, F. J. DORIA, R. T. Rodrigo Trevisoli Doria |
author_role |
author |
author2 |
DORIA, R. T. Rodrigo Trevisoli Doria |
author2_role |
author author |
dc.contributor.author.fl_str_mv |
COSTA, F. J. DORIA, R. T. Rodrigo Trevisoli Doria |
dc.subject.por.fl_str_mv |
SOI UTBB Self-Heating Thermal Resistance Thermal-Coupling |
topic |
SOI UTBB Self-Heating Thermal Resistance Thermal-Coupling |
description |
The main goal of this work is to perform a first-time analysis of the thermal cross-coupling in a system composed by some devices in an integration node degree composed by advanced UTBB SOI MOSFETs through numerical simulations, validated with experimental data from the literature. In this analysis, it could be observed that devices located on the channel length direction provoke a reduced thermal coupling and devices with their drain region next to each other suffer of an increased thermal coupling due to the lumped thermal energy. It also could be observed a degradation in some electrical parameters and in the thermal properties of a device under the influence of surrounded devices biased. |
publishDate |
2020 |
dc.date.issued.fl_str_mv |
2020-07-31 |
dc.date.accessioned.fl_str_mv |
2021-11-25T22:33:31Z |
dc.date.available.fl_str_mv |
2021-11-25T22:33:31Z |
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info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/article |
format |
article |
status_str |
publishedVersion |
dc.identifier.citation.fl_str_mv |
COSTA, F. J.; TREVISOLI, R.; DORIA, R. T.. UTBB MOSFETs Thermal Coupling Analysis in Technological Node Level. JICS. JOURNAL OF INTEGRATED CIRCUITS AND SYSTEMS (ED. PORTUGUÊS), v. 15, n. 2, p. 1-5, 2020. |
dc.identifier.uri.fl_str_mv |
https://repositorio.fei.edu.br/handle/FEI/3479 |
dc.identifier.issn.none.fl_str_mv |
1807-1953 |
dc.identifier.doi.none.fl_str_mv |
10.29292/jics.v15i2.194 |
identifier_str_mv |
COSTA, F. J.; TREVISOLI, R.; DORIA, R. T.. UTBB MOSFETs Thermal Coupling Analysis in Technological Node Level. JICS. JOURNAL OF INTEGRATED CIRCUITS AND SYSTEMS (ED. PORTUGUÊS), v. 15, n. 2, p. 1-5, 2020. 1807-1953 10.29292/jics.v15i2.194 |
url |
https://repositorio.fei.edu.br/handle/FEI/3479 |
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JICS. JOURNAL OF INTEGRATED CIRCUITS AND SYSTEMS (ED. PORTUGUÊS) |
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openAccess |
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