Core LDPC para o padrão DVB-S2 - Digital Video Broadcasting - Satellite Generation 2

• Autor(a) principal: Mengarda, Augusto Calcanhotto
• Data de Publicação: 2016
• Tipo de documento: Dissertação
• Idioma: por
• Título da fonte: Biblioteca Digital de Teses e Dissertações da PUC_RS
• Texto Completo: http://tede2.pucrs.br/tede2/handle/tede/7061
• topic: CODIFICAÇÃO; TELECOMUNICAÇÕES; ENGENHARIA ELÉTRICA; ENGENHARIAS

Digital Video Broadcasting – Satellite Generation 2 (DVB-S2) standard is widely adopted for militar and civil communication. Due to the long distance between transmitter and receiver, satellite communication links operate with low signal to noise ratio. Forward Error Correction (FEC) techniques are of particular importance for DVBS2 systems, ensuring the desired performance. This dissertation presents the development of a core, in hardware description language, of a LDPC (Low-Density Parity-Check) codec compatible with the DVB-S2 standard. The developed core operates with two sizes of frames and twenty-one encoding rates, as defined in the DVB-S2 standard. The dissertation addresses the main challenges regarding the codec implementation and how they are faced. Three versions of the proposed architecture are implemented and evaluated. Each version uses a different numerical representation for the codec variables. VHDL simulation results are compared with simulations in C programming language, which uses floating point. The results show that the proposed core has equivalent or superior performance to those works reported in the literature when using the architecture with the smallest numerical representation. However, when evaluated the architecture with the highest numerical representation, the obtained FEC performance is significantly better than those presented in the literature, and are close to the results obtained with 64 bits floating point representation. In addition to the performance evaluation, the use of the FPGA (Field-Programmable Gate Array) resources are presented for each one of the three implemented architectures. The analysis of performance versus FPGA resources is addressed.