3D network-on-chip architectural exploration

• Autor(a) principal: Souza, Yan Ghidini de
• Data de Publicação: 2014
• Tipo de documento: Dissertação
• Idioma: por
• Título da fonte: Biblioteca Digital de Teses e Dissertações da PUC_RS
• Texto Completo: http://tede2.pucrs.br/tede2/handle/tede/5254
• topic: INFORMÁTICA; ARQUITETURA DE COMPUTADOR; MULTIPROCESSADORES; CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO

Communication plays a crucial role in high performance design of Multiprocessor Systems-on-Chips (MPSoCs). Accordingly, Networks-on-Chip (NoCs) have been proposed as a solution to deal with the global communication of complex MPSoCs. NoC-based architectures are characterized by various tradeoffs related to structural characteristics, performance specifications, and application demands. Additionally, wire delay and power dissipation are rising as the number of cores over a 2D (two-dimensional) plane increases. One of the reasons for that is the long network diameter and overall communication distance. In this scenario, 3D (three-dimensional) Integrated Circuit (IC) technology applied to NoC architectures allows greater device integration, shorter interconnection, and it aims to reduce the length and number of global interconnections (interconnections among every processing element), which directly influences on the communication performance and allows opportunities for chip architecture innovations. Moreover, 3D NoC-based architectures appear as alternative to reduce network latency, energy consumption and area footprint in comparison to 2D NoC topologies. Albeit a wide variety of technologies is available for 3D interconnection, the employment of Through Silicon Vias (TSVs) is a feasible approach for the interconnection between stacked layers. However, the drawback for current 3D technologies is that TSVs are usually very expensive in terms of silicon area limiting their usage. This work presents a 3D mesh NoC architecture called Lasio, exploring architectural impacts of 3D versus 2D NoC topologies on latency, throughput, and buffers occupancy. It also analyzes the influence of buffer depth on communication latency and on application latency. Such evaluations considered varied network parameters, such as traffic patterns, buffer depth, TSVs serialization level, and a range of packet sizes. Besides, during this work, it was implemented a TSV serialization scheme on the Lasio NoC, and it was analyzed the impact of such serialization scheme on area cost, power dissipation, network and application latency, and occupancy on buffers of input ports for a 4x4x4 3D mesh NoCs with different serialization degrees. Experimental results show that, in average, 3D topologies minimize 30% the application latency and increase 56% the packets throughput, when compared to 2D topologies. In addition, this work highlights that when applying an appropriate buffer depth, the application latency is reduced up to 3.4 times for 2D topologies and 2.3 times for 3D topologies. Additional results demonstrate that NoCs 3D approach reduce the links occupancy when compared to 2D counterpart, which potentially leads to higher throughput and more dissipation power and latency efficiency. Moreover, results also demonstrate that the proposed serialization scheme allows reducing TSVs usage with low performance cost, displaying the potential benefits of the scheme in 3D NoC-based MPSoCs.