Designing a sigma-delta modulator using passive integrators and calibration

• Autor(a) principal: Martins, Diogo Filipe da Cruz
• Data de Publicação: 2023
• Tipo de documento: Dissertação
• Idioma: eng
• Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
• Texto Completo: http://hdl.handle.net/10362/164581
• topic: Analog to Digital Converter (ADC); Sigma-Delta Modulator (ΣΔM); 2-1MASH ΣΔM; Calibration; Genetic Algorithm; Domínio/Área Científica::Engenharia e Tecnologia::Nanotecnologia

An Analog to Digital Converter (ADC) serves as vital components bridging the analog and digital domains,facilitating the conversion of real-world data into digital format. Due to its essential role across various applications, the ADC is extensively researched in electronics. Ensuring their performance remains aligned with the ever-evolving technological landscape is crucial. To achieve this, optimization algorithms are employed to enhance architectural efficiency. This study explores the potential of a passive 2-1 Multi-stAge noise SHaping (MASH) Sigma-Delta Modulator (ΣΔM) architecture as presented in[2], complemented by calibration techniques detailed in [3]. Although the architecture [2] has previously undergone optimization,calibration has not been used. The introduction of calibration methods has the potential to improve performance. To tackle this issue, a genetic algorithm was implemented using the pre-existing MATLAB® code with modifications. Additionally, a C++ code was developed to enhance speed, enabling a more thorough analysis. The primary objective was to enhance the 2-1 MASH ΣΔM while minimizing Signal-to-Noise-and-Distortion Ratio (SNDR) degradation in the presence of process variations. Monte Carlo simulations were conducted to validate performance improvements. This thesis proposes a redesigned 2-1 MASH ΣΔM based on [3].