A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP
Autor(a) principal: | |
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Data de Publicação: | 2023 |
Outros Autores: | , , , , |
Tipo de documento: | Artigo |
Idioma: | eng |
Título da fonte: | Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
Texto Completo: | http://hdl.handle.net/10400.26/44198 |
Resumo: | The increasing complexity of System-on-Chip (SoC) and the ongoing technology miniaturization on Integrated Circuit (IC) manufacturing processes makes modern SoCs more susceptible to Single-Event Effects (SEE) caused by radiation, even at sea level. To provide realistic estimates at a low cost, efficient analysis techniques capable of replicating SEEs are required. Among these methods, fault injection through emulation using Field-Programmable Gate Array (FPGA) enables campaigns to be run on a Circuit Under Test (CUT). This paper investigates the use of an FPGA architecture to speed up the execution of fault campaigns. As a result, a new methodology for mapping the CUT occupation on the FPGA is proposed, significantly reducing the total number of faults to be injected. In addition, a fault injection technique/flow is proposed to demonstrate the benefits of cutting-edge approaches. The presented technique emulates Single-Event Transient (SET) in all combinatorial elements of the CUT using the Internal Configuration Access Port (ICAP) of Xilinx FPGAs. |
id |
RCAP_1aa09c62403a553efdf433a364fe76b0 |
---|---|
oai_identifier_str |
oai:comum.rcaap.pt:10400.26/44198 |
network_acronym_str |
RCAP |
network_name_str |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
repository_id_str |
7160 |
spelling |
A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAPSETfault injectionLEON3FPGAspace applicationsCAPThe increasing complexity of System-on-Chip (SoC) and the ongoing technology miniaturization on Integrated Circuit (IC) manufacturing processes makes modern SoCs more susceptible to Single-Event Effects (SEE) caused by radiation, even at sea level. To provide realistic estimates at a low cost, efficient analysis techniques capable of replicating SEEs are required. Among these methods, fault injection through emulation using Field-Programmable Gate Array (FPGA) enables campaigns to be run on a Circuit Under Test (CUT). This paper investigates the use of an FPGA architecture to speed up the execution of fault campaigns. As a result, a new methodology for mapping the CUT occupation on the FPGA is proposed, significantly reducing the total number of faults to be injected. In addition, a fault injection technique/flow is proposed to demonstrate the benefits of cutting-edge approaches. The presented technique emulates Single-Event Transient (SET) in all combinatorial elements of the CUT using the Internal Configuration Access Port (ICAP) of Xilinx FPGAs.Repositório ComumFerlini, FredericoViel, FelipeSeman, Laio OrielHector PettenghiBezerra, EduardoLEITHARDT, VALDERI2023-03-17T10:40:07Z2023-02-062023-02-09T10:44:31Z2023-02-06T00:00:00Zinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfhttp://hdl.handle.net/10400.26/44198engcv-prod-313821710.3390/electronics12040807info:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2023-05-04T10:30:26Zoai:comum.rcaap.pt:10400.26/44198Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireopendoar:71602024-03-19T17:45:09.760007Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse |
dc.title.none.fl_str_mv |
A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP |
title |
A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP |
spellingShingle |
A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP Ferlini, Frederico SET fault injection LEON3 FPGA space applications CAP |
title_short |
A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP |
title_full |
A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP |
title_fullStr |
A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP |
title_full_unstemmed |
A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP |
title_sort |
A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP |
author |
Ferlini, Frederico |
author_facet |
Ferlini, Frederico Viel, Felipe Seman, Laio Oriel Hector Pettenghi Bezerra, Eduardo LEITHARDT, VALDERI |
author_role |
author |
author2 |
Viel, Felipe Seman, Laio Oriel Hector Pettenghi Bezerra, Eduardo LEITHARDT, VALDERI |
author2_role |
author author author author author |
dc.contributor.none.fl_str_mv |
Repositório Comum |
dc.contributor.author.fl_str_mv |
Ferlini, Frederico Viel, Felipe Seman, Laio Oriel Hector Pettenghi Bezerra, Eduardo LEITHARDT, VALDERI |
dc.subject.por.fl_str_mv |
SET fault injection LEON3 FPGA space applications CAP |
topic |
SET fault injection LEON3 FPGA space applications CAP |
description |
The increasing complexity of System-on-Chip (SoC) and the ongoing technology miniaturization on Integrated Circuit (IC) manufacturing processes makes modern SoCs more susceptible to Single-Event Effects (SEE) caused by radiation, even at sea level. To provide realistic estimates at a low cost, efficient analysis techniques capable of replicating SEEs are required. Among these methods, fault injection through emulation using Field-Programmable Gate Array (FPGA) enables campaigns to be run on a Circuit Under Test (CUT). This paper investigates the use of an FPGA architecture to speed up the execution of fault campaigns. As a result, a new methodology for mapping the CUT occupation on the FPGA is proposed, significantly reducing the total number of faults to be injected. In addition, a fault injection technique/flow is proposed to demonstrate the benefits of cutting-edge approaches. The presented technique emulates Single-Event Transient (SET) in all combinatorial elements of the CUT using the Internal Configuration Access Port (ICAP) of Xilinx FPGAs. |
publishDate |
2023 |
dc.date.none.fl_str_mv |
2023-03-17T10:40:07Z 2023-02-06 2023-02-09T10:44:31Z 2023-02-06T00:00:00Z |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/article |
format |
article |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://hdl.handle.net/10400.26/44198 |
url |
http://hdl.handle.net/10400.26/44198 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.none.fl_str_mv |
cv-prod-3138217 10.3390/electronics12040807 |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.format.none.fl_str_mv |
application/pdf |
dc.source.none.fl_str_mv |
reponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação instacron:RCAAP |
instname_str |
Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação |
instacron_str |
RCAAP |
institution |
RCAAP |
reponame_str |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
collection |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
repository.name.fl_str_mv |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação |
repository.mail.fl_str_mv |
|
_version_ |
1799131536768892928 |