Efficient hardware design and implementation of the voting scheme-based convolution

Detalhes bibliográficos
Autor(a) principal: Pereira, Pedro Miguel Coelho
Data de Publicação: 2022
Outros Autores: Silva, João Pedro Duarte, Silva, António, Fernandes, Duarte, Machado, Rui
Tipo de documento: Artigo
Idioma: eng
Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
Texto Completo: https://hdl.handle.net/1822/79819
Resumo: Due to a point cloud’s sparse nature, a sparse convolution block design is necessary to deal with its particularities. Mechanisms adopted in computer vision have recently explored the advantages of data processing in more energy-efficient hardware, such as the FPGA, as a response to the need to run these algorithms on resource-constrained edge devices. However, implementing it in hardware has not been properly explored, resulting in a small number of studies aimed at analyzing the potential of sparse convolutions and their efficiency on resource-constrained hardware platforms. This article presents the design of a customizable hardware block for the voting convolution. We carried out an in-depth analysis to determine under which conditions the use of the voting scheme is justified instead of dense convolutions. The proposed hardware design achieves an energy consumption about 8.7 times lower than similar works in the literature by ignoring unnecessary arithmetic operations with null weights and leveraging data dependency. Access to data memory was also reduced to the minimum necessary, leading to improvements of around 55% in processing time. To evaluate both the performance and applicability of the proposed solution, the voting convolution was integrated into the well-known PointPillars model, where it achieves improvements between 23.05% and 80.44% without a significant effect on detection performance.
id RCAP_20454d6c58b26bff5f727012828e22fd
oai_identifier_str oai:repositorium.sdum.uminho.pt:1822/79819
network_acronym_str RCAP
network_name_str Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
repository_id_str 7160
spelling Efficient hardware design and implementation of the voting scheme-based convolutionfield-programmable gate array (FPGA)sparsityvoting convolution3D object detection modelsdeep learningCiências Naturais::Ciências da Computação e da InformaçãoScience & TechnologyDue to a point cloud’s sparse nature, a sparse convolution block design is necessary to deal with its particularities. Mechanisms adopted in computer vision have recently explored the advantages of data processing in more energy-efficient hardware, such as the FPGA, as a response to the need to run these algorithms on resource-constrained edge devices. However, implementing it in hardware has not been properly explored, resulting in a small number of studies aimed at analyzing the potential of sparse convolutions and their efficiency on resource-constrained hardware platforms. This article presents the design of a customizable hardware block for the voting convolution. We carried out an in-depth analysis to determine under which conditions the use of the voting scheme is justified instead of dense convolutions. The proposed hardware design achieves an energy consumption about 8.7 times lower than similar works in the literature by ignoring unnecessary arithmetic operations with null weights and leveraging data dependency. Access to data memory was also reduced to the minimum necessary, leading to improvements of around 55% in processing time. To evaluate both the performance and applicability of the proposed solution, the voting convolution was integrated into the well-known PointPillars model, where it achieves improvements between 23.05% and 80.44% without a significant effect on detection performance.European Structural and Investment Funds in the FEDER component, through the Operational Competitiveness and Internationalization Programme (COMPETE 2020) (Project no. 037902; Funding Reference: POCI-01-0247-FEDER-037902).Multidisciplinary Digital Publishing InstituteUniversidade do MinhoPereira, Pedro Miguel CoelhoSilva, João Pedro DuarteSilva, AntónioFernandes, DuarteMachado, Rui2022-04-122022-04-12T00:00:00Zinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfhttps://hdl.handle.net/1822/79819engPereira, P.; Silva, J.; Silva, A.; Fernandes, D.; Machado, R. Efficient Hardware Design and Implementation of the Voting Scheme-Based Convolution. Sensors 2022, 22, 2943. https://doi.org/10.3390/s220829431424-82201424-822010.3390/s2208294335458928https://www.mdpi.com/1424-8220/22/8/2943info:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2023-07-21T12:44:13Zoai:repositorium.sdum.uminho.pt:1822/79819Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireopendoar:71602024-03-19T19:41:52.401520Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse
dc.title.none.fl_str_mv Efficient hardware design and implementation of the voting scheme-based convolution
title Efficient hardware design and implementation of the voting scheme-based convolution
spellingShingle Efficient hardware design and implementation of the voting scheme-based convolution
Pereira, Pedro Miguel Coelho
field-programmable gate array (FPGA)
sparsity
voting convolution
3D object detection models
deep learning
Ciências Naturais::Ciências da Computação e da Informação
Science & Technology
title_short Efficient hardware design and implementation of the voting scheme-based convolution
title_full Efficient hardware design and implementation of the voting scheme-based convolution
title_fullStr Efficient hardware design and implementation of the voting scheme-based convolution
title_full_unstemmed Efficient hardware design and implementation of the voting scheme-based convolution
title_sort Efficient hardware design and implementation of the voting scheme-based convolution
author Pereira, Pedro Miguel Coelho
author_facet Pereira, Pedro Miguel Coelho
Silva, João Pedro Duarte
Silva, António
Fernandes, Duarte
Machado, Rui
author_role author
author2 Silva, João Pedro Duarte
Silva, António
Fernandes, Duarte
Machado, Rui
author2_role author
author
author
author
dc.contributor.none.fl_str_mv Universidade do Minho
dc.contributor.author.fl_str_mv Pereira, Pedro Miguel Coelho
Silva, João Pedro Duarte
Silva, António
Fernandes, Duarte
Machado, Rui
dc.subject.por.fl_str_mv field-programmable gate array (FPGA)
sparsity
voting convolution
3D object detection models
deep learning
Ciências Naturais::Ciências da Computação e da Informação
Science & Technology
topic field-programmable gate array (FPGA)
sparsity
voting convolution
3D object detection models
deep learning
Ciências Naturais::Ciências da Computação e da Informação
Science & Technology
description Due to a point cloud’s sparse nature, a sparse convolution block design is necessary to deal with its particularities. Mechanisms adopted in computer vision have recently explored the advantages of data processing in more energy-efficient hardware, such as the FPGA, as a response to the need to run these algorithms on resource-constrained edge devices. However, implementing it in hardware has not been properly explored, resulting in a small number of studies aimed at analyzing the potential of sparse convolutions and their efficiency on resource-constrained hardware platforms. This article presents the design of a customizable hardware block for the voting convolution. We carried out an in-depth analysis to determine under which conditions the use of the voting scheme is justified instead of dense convolutions. The proposed hardware design achieves an energy consumption about 8.7 times lower than similar works in the literature by ignoring unnecessary arithmetic operations with null weights and leveraging data dependency. Access to data memory was also reduced to the minimum necessary, leading to improvements of around 55% in processing time. To evaluate both the performance and applicability of the proposed solution, the voting convolution was integrated into the well-known PointPillars model, where it achieves improvements between 23.05% and 80.44% without a significant effect on detection performance.
publishDate 2022
dc.date.none.fl_str_mv 2022-04-12
2022-04-12T00:00:00Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/article
format article
status_str publishedVersion
dc.identifier.uri.fl_str_mv https://hdl.handle.net/1822/79819
url https://hdl.handle.net/1822/79819
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv Pereira, P.; Silva, J.; Silva, A.; Fernandes, D.; Machado, R. Efficient Hardware Design and Implementation of the Voting Scheme-Based Convolution. Sensors 2022, 22, 2943. https://doi.org/10.3390/s22082943
1424-8220
1424-8220
10.3390/s22082943
35458928
https://www.mdpi.com/1424-8220/22/8/2943
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv Multidisciplinary Digital Publishing Institute
publisher.none.fl_str_mv Multidisciplinary Digital Publishing Institute
dc.source.none.fl_str_mv reponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
instacron:RCAAP
instname_str Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
instacron_str RCAAP
institution RCAAP
reponame_str Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
collection Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
repository.name.fl_str_mv Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
repository.mail.fl_str_mv
_version_ 1799132969295675392