Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems

Detalhes bibliográficos
Autor(a) principal: João Bispo
Data de Publicação: 2013
Outros Autores: Nuno Miguel Paulino, João Paiva Cardoso, João Canas Ferreira
Tipo de documento: Artigo
Idioma: eng
Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
Texto Completo: http://repositorio.inesctec.pt/handle/123456789/5564
http://dx.doi.org/10.1109/tii.2012.2235844
Resumo: This paper presents a novel approach to accelerate program execution by mapping repetitive traces of executed instructions, called Megablocks, to a runtime reconfigurable array of functional units. An offline tool suite extracts Megablocks from microprocessor instruction traces and generates a Reconfigurable Processing Unit (RPU) tailored for the execution of those Megablocks. The system is able to transparently movebcomputations from the microprocessor to the RPU at runtime. A prototype implementation of the system using a cacheless MicroBlaze microprocessor running code located in external memory reaches speedups from 2.2x to 18.2x for a set of 14 benchmark kernels. For a system setup which maximizes microprocessor performance by having the application code located in internal block RAMs, speedups from 1.4x to 2.8x were estimated.
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spelling Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW SystemsThis paper presents a novel approach to accelerate program execution by mapping repetitive traces of executed instructions, called Megablocks, to a runtime reconfigurable array of functional units. An offline tool suite extracts Megablocks from microprocessor instruction traces and generates a Reconfigurable Processing Unit (RPU) tailored for the execution of those Megablocks. The system is able to transparently movebcomputations from the microprocessor to the RPU at runtime. A prototype implementation of the system using a cacheless MicroBlaze microprocessor running code located in external memory reaches speedups from 2.2x to 18.2x for a set of 14 benchmark kernels. For a system setup which maximizes microprocessor performance by having the application code located in internal block RAMs, speedups from 1.4x to 2.8x were estimated.2018-01-05T17:11:27Z2013-01-01T00:00:00Z2013info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfhttp://repositorio.inesctec.pt/handle/123456789/5564http://dx.doi.org/10.1109/tii.2012.2235844engJoão BispoNuno Miguel PaulinoJoão Paiva CardosoJoão Canas Ferreirainfo:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2023-05-15T10:20:50Zoai:repositorio.inesctec.pt:123456789/5564Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireopendoar:71602024-03-19T17:53:41.088602Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse
dc.title.none.fl_str_mv Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems
title Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems
spellingShingle Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems
João Bispo
title_short Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems
title_full Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems
title_fullStr Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems
title_full_unstemmed Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems
title_sort Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems
author João Bispo
author_facet João Bispo
Nuno Miguel Paulino
João Paiva Cardoso
João Canas Ferreira
author_role author
author2 Nuno Miguel Paulino
João Paiva Cardoso
João Canas Ferreira
author2_role author
author
author
dc.contributor.author.fl_str_mv João Bispo
Nuno Miguel Paulino
João Paiva Cardoso
João Canas Ferreira
description This paper presents a novel approach to accelerate program execution by mapping repetitive traces of executed instructions, called Megablocks, to a runtime reconfigurable array of functional units. An offline tool suite extracts Megablocks from microprocessor instruction traces and generates a Reconfigurable Processing Unit (RPU) tailored for the execution of those Megablocks. The system is able to transparently movebcomputations from the microprocessor to the RPU at runtime. A prototype implementation of the system using a cacheless MicroBlaze microprocessor running code located in external memory reaches speedups from 2.2x to 18.2x for a set of 14 benchmark kernels. For a system setup which maximizes microprocessor performance by having the application code located in internal block RAMs, speedups from 1.4x to 2.8x were estimated.
publishDate 2013
dc.date.none.fl_str_mv 2013-01-01T00:00:00Z
2013
2018-01-05T17:11:27Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/article
format article
status_str publishedVersion
dc.identifier.uri.fl_str_mv http://repositorio.inesctec.pt/handle/123456789/5564
http://dx.doi.org/10.1109/tii.2012.2235844
url http://repositorio.inesctec.pt/handle/123456789/5564
http://dx.doi.org/10.1109/tii.2012.2235844
dc.language.iso.fl_str_mv eng
language eng
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
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dc.source.none.fl_str_mv reponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
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instacron:RCAAP
instname_str Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
instacron_str RCAAP
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repository.name.fl_str_mv Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
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