Programmable Logic Devices: a test approach for the input / output pad-to-pin interconnections

• Autor(a) principal: Gericota, Manuel G.
• Data de Publicação: 2003
• Outros Autores: Alves, Gustavo R., Silva, Miguel L., Ferreira, J. M. Martins
• Tipo de documento: Artigo
• Idioma: eng
• Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
• Texto Completo: http://hdl.handle.net/10400.22/9726
• topic: Programmable Logic Devices (PLDs); Boundary Scan Test; Input/Output Blocks (IOBs)

In the last few years, an increasing use of Programmable Logic Devices (PLDs) in the development of new embedded and systems-on-a-chip (SoC) solutions created the need of new test procedures for this kind of components. Several approaches, depending on the type of PLDs used, were proposed in the literature, addressing the test of the configurable logic array, the interconnection arrays and the configuration memory. However, very little work has been done concerning the specific test of Input/Output Blocks (IOBs) and pad-to-pin bonds. In this paper, a method aimed at covering the test of the IOBs structure in reprogrammable PLDs is proposed. The interconnections between IOBs and other components or connectors at board level are also targeted, benefiting from the availability of Boundary Scan Test (BST) cells on the IOBs of the major PLD families and from the use of “active connectors”.