Design of a Reed Solomon encoder and decoder

• Autor(a) principal: Cardoso, Gonçalo Nuno Veleirinho
• Data de Publicação: 2022
• Tipo de documento: Dissertação
• Idioma: eng
• Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
• Texto Completo: http://hdl.handle.net/10773/37888
• topic: Digital design; Verilog; Reed Solomon; Encoder; Decoder; ASIC; FPGA; Frequency optimization

Reed Solomon codes have been widely used in the technological era, in applications such as the data transmission storage units and PCs and between chips. These are error correction codes, used in communication channels that typically affect the system with high density errors. The developed work aimed at developing two Reed Solomon IP Cores: an encoder and a decoder. While developing these, some practical considerations to provide higher operation frequencies (at the cost of small increases in latency) were deployed and a state-of-the-art KES block for the decoder was used, by implementing the ePIBMA algorithm. The main objective of this work was to analyze and compare different technologies, using different FPGAs and one ASIC implementation. The results of more importance have been the comparison in performance between the FPGAs and the ASIC, where it was observed that the maximum operating frequency is 18.5 times higher in the encoder and 19.2 times higher in the decoder of the ASIC implementation. These results contribute to the literature with a comparison between these implementations, which is not usually presented.