Modeling high bitrate communication interfaces with MatLab®

• Autor(a) principal: Malafaia, Frederico Rafael Teixeira
• Data de Publicação: 2014
• Tipo de documento: Dissertação
• Idioma: eng
• Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
• Texto Completo: http://hdl.handle.net/10773/14543
• topic: Engenharia electrónica; Transmissão de dados; Recuperação de dados

Now-a-days, high-speed digital data transmission is under continuous development. The constant increasing on the bitrates has been lead to the need of more sophisticated and complex receivers, systems that provide the recovering of the transmitted data over a dispersive channel that degrades the transmitted signal quality. Therefore, the receiver shall compensate the distortion introduced by the channel as well as synchronize the received signal that in addition to distortion, is also affected by jitter. The distortion derived from the channel is attenuated by means of equalization circuits that offset the channel frequency response at the transmission rate, making it as flat as possible for the desired frequency. On the other hand, the synchronization of the received signal is achieved by means of clock and data recovery circuits that usually recover the clock signal through the data transitions for sampling the received data. The main focus of this thesis concerns the modeling of a data receiver for a high-speed interface. The simulation of the data receiver block implies the modeling of a transmission channel depending on its characteristics. The proposed transmission system, from the transmitter to the output of the data recovery block, includes equalization filters for signal conditioning, of which several distinct architectures are studied. It’s proposed two architectures for the clock and data recovery circuit. The first one is a 2x oversampling clock and data recovery circuit based on a Phase Tracking architecture. The second one, is a 3x oversampling clock and data recovery based on a Blind Sampling architecture. By modeling both of the architectures of the clock and data recovery circuit, it’s intended to analyze the respective jitter tolerance results. It is crucial to know the amount of jitter that can be tolerated by these circuits in order to recover the data with a satisfying bit error ratio. The obtained results show a very close match to the theoretical values, where the 2x and 3x oversampling architecture presents a jitter tolerance of, approximately, 12UI and 23UI respectively for low jitter frequencies.