Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact)

Detalhes bibliográficos
Autor(a) principal: Awan, Muhammad Ali
Data de Publicação: 2018
Outros Autores: Souto, Pedro, Bletsas, Konstantinos, Åkesson, Benny, Tovar, Eduardo
Tipo de documento: Artigo
Idioma: eng
Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
Texto Completo: http://hdl.handle.net/10400.22/12541
Resumo: This artifact demonstrates the performance of the proposed worst-case memory stall analysis for a memory-regulated multicore with two memory controllers. The memory stall analysis is implemented in Java along with five different stall-cognisant bandwidth-to-core and task-to-core assignment heuristics. It evaluates the performance of these heuristics in terms of schedulability via experiments with synthetic task sets capturing different system characteristics. It also quantifies the cost in terms of extra stall for letting all cores benefit from the memory space offered by both controllers on the given multicore platform.
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spelling Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact)Multiple memory controllersMemory regulationMulticoreThis artifact demonstrates the performance of the proposed worst-case memory stall analysis for a memory-regulated multicore with two memory controllers. The memory stall analysis is implemented in Java along with five different stall-cognisant bandwidth-to-core and task-to-core assignment heuristics. It evaluates the performance of these heuristics in terms of schedulability via experiments with synthetic task sets capturing different system characteristics. It also quantifies the cost in terms of extra stall for letting all cores benefit from the memory space offered by both controllers on the given multicore platform.Schloss Dagstuhl--Leibniz-Zentrum fuer InformatikRepositório Científico do Instituto Politécnico do PortoAwan, Muhammad AliSouto, PedroBletsas, KonstantinosÅkesson, BennyTovar, Eduardo2019-01-04T15:19:50Z20182018-01-01T00:00:00Zinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfhttp://hdl.handle.net/10400.22/12541eng2509-819510.4230/DARTS.4.2.5info:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2023-03-13T12:54:28Zoai:recipp.ipp.pt:10400.22/12541Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireopendoar:71602024-03-19T17:32:48.449109Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse
dc.title.none.fl_str_mv Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact)
title Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact)
spellingShingle Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact)
Awan, Muhammad Ali
Multiple memory controllers
Memory regulation
Multicore
title_short Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact)
title_full Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact)
title_fullStr Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact)
title_full_unstemmed Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact)
title_sort Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact)
author Awan, Muhammad Ali
author_facet Awan, Muhammad Ali
Souto, Pedro
Bletsas, Konstantinos
Åkesson, Benny
Tovar, Eduardo
author_role author
author2 Souto, Pedro
Bletsas, Konstantinos
Åkesson, Benny
Tovar, Eduardo
author2_role author
author
author
author
dc.contributor.none.fl_str_mv Repositório Científico do Instituto Politécnico do Porto
dc.contributor.author.fl_str_mv Awan, Muhammad Ali
Souto, Pedro
Bletsas, Konstantinos
Åkesson, Benny
Tovar, Eduardo
dc.subject.por.fl_str_mv Multiple memory controllers
Memory regulation
Multicore
topic Multiple memory controllers
Memory regulation
Multicore
description This artifact demonstrates the performance of the proposed worst-case memory stall analysis for a memory-regulated multicore with two memory controllers. The memory stall analysis is implemented in Java along with five different stall-cognisant bandwidth-to-core and task-to-core assignment heuristics. It evaluates the performance of these heuristics in terms of schedulability via experiments with synthetic task sets capturing different system characteristics. It also quantifies the cost in terms of extra stall for letting all cores benefit from the memory space offered by both controllers on the given multicore platform.
publishDate 2018
dc.date.none.fl_str_mv 2018
2018-01-01T00:00:00Z
2019-01-04T15:19:50Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/article
format article
status_str publishedVersion
dc.identifier.uri.fl_str_mv http://hdl.handle.net/10400.22/12541
url http://hdl.handle.net/10400.22/12541
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv 2509-8195
10.4230/DARTS.4.2.5
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik
publisher.none.fl_str_mv Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik
dc.source.none.fl_str_mv reponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
instacron:RCAAP
instname_str Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
instacron_str RCAAP
institution RCAAP
reponame_str Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
collection Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
repository.name.fl_str_mv Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
repository.mail.fl_str_mv
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