Custom ASIC design for SHA-256 using open-source tools

• Autor(a) principal: Franck, Lucas Daudt
• Data de Publicação: 2024
• Outros Autores: Ginja, Gabriel Augusto, Carmo, João Paulo, Afonso, José A., Luppe, Maximiliam
• Tipo de documento: Artigo
• Idioma: eng
• Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
• Texto Completo: https://hdl.handle.net/1822/89307
• topic: Open-source EDA tools; ASIC; Hardware accelerator; SHA-256; Cryptography; Engenharia e Tecnologia::Engenharia Eletrotécnica, Eletrónica e Informática; Indústria, inovação e infraestruturas

The growth of digital communications has driven the development of numerous cryptographic methods for secure data transfer and storage. The SHA-256 algorithm is a cryptographic hash function widely used for validating data authenticity, identity, and integrity. The inherent SHA-256 computational overhead has motivated the search for more efficient hardware solutions, such as application-specific integrated circuits (ASICs). This work presents a custom ASIC hardware accelerator for the SHA-256 algorithm entirely created using open-source electronic design automation tools. The integrated circuit was synthesized using SkyWater SKY130 130 nm process technology through the OpenLANE automated workflow. The proposed final design is compatible with 32-bit microcontrollers, has a total area of 104,585 µm2, and operates at a maximum clock frequency of 97.9 MHz. Several optimization configurations were tested and analyzed during the synthesis phase to enhance the performance of the final design.