Logic circuits synthesis through genetic algorithms

Detalhes bibliográficos
Autor(a) principal: Reis, Cecília
Data de Publicação: 2005
Outros Autores: Tenreiro Machado, J. A., Cunha, J. Boaventura
Tipo de documento: Artigo
Idioma: eng
Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
Texto Completo: http://hdl.handle.net/10400.22/13486
Resumo: This paper proposes a genetic algorithm for designing combinational logic circuits and studies four different case examples: the 2-to-1 multiplexer, the one-bit full adder, the four-bit parity checker and the two-bit multiplier. The objective of this work is to generate a functional circuit with the minimum number of logic gates. It is also studied the scalability problem that emerges from the exponential growth of the truth table when the circuits complexity increases. Furthermore, it is as well investigated the population size and the processing time for achieving a solution in order to establish a compromise between the two parameters.
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spelling Logic circuits synthesis through genetic algorithmsComputer-aided designGenetic algorithmsCircuit designCombinational logic circuitsThis paper proposes a genetic algorithm for designing combinational logic circuits and studies four different case examples: the 2-to-1 multiplexer, the one-bit full adder, the four-bit parity checker and the two-bit multiplier. The objective of this work is to generate a functional circuit with the minimum number of logic gates. It is also studied the scalability problem that emerges from the exponential growth of the truth table when the circuits complexity increases. Furthermore, it is as well investigated the population size and the processing time for achieving a solution in order to establish a compromise between the two parameters.Repositório Científico do Instituto Politécnico do PortoReis, CecíliaTenreiro Machado, J. A.Cunha, J. Boaventura2019-04-09T10:27:26Z2005-052005-05-01T00:00:00Zinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfhttp://hdl.handle.net/10400.22/13486eng1790-0832info:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2023-03-13T12:49:02Zoai:recipp.ipp.pt:10400.22/13486Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireopendoar:71602024-03-19T17:28:45.265256Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse
dc.title.none.fl_str_mv Logic circuits synthesis through genetic algorithms
title Logic circuits synthesis through genetic algorithms
spellingShingle Logic circuits synthesis through genetic algorithms
Reis, Cecília
Computer-aided design
Genetic algorithms
Circuit design
Combinational logic circuits
title_short Logic circuits synthesis through genetic algorithms
title_full Logic circuits synthesis through genetic algorithms
title_fullStr Logic circuits synthesis through genetic algorithms
title_full_unstemmed Logic circuits synthesis through genetic algorithms
title_sort Logic circuits synthesis through genetic algorithms
author Reis, Cecília
author_facet Reis, Cecília
Tenreiro Machado, J. A.
Cunha, J. Boaventura
author_role author
author2 Tenreiro Machado, J. A.
Cunha, J. Boaventura
author2_role author
author
dc.contributor.none.fl_str_mv Repositório Científico do Instituto Politécnico do Porto
dc.contributor.author.fl_str_mv Reis, Cecília
Tenreiro Machado, J. A.
Cunha, J. Boaventura
dc.subject.por.fl_str_mv Computer-aided design
Genetic algorithms
Circuit design
Combinational logic circuits
topic Computer-aided design
Genetic algorithms
Circuit design
Combinational logic circuits
description This paper proposes a genetic algorithm for designing combinational logic circuits and studies four different case examples: the 2-to-1 multiplexer, the one-bit full adder, the four-bit parity checker and the two-bit multiplier. The objective of this work is to generate a functional circuit with the minimum number of logic gates. It is also studied the scalability problem that emerges from the exponential growth of the truth table when the circuits complexity increases. Furthermore, it is as well investigated the population size and the processing time for achieving a solution in order to establish a compromise between the two parameters.
publishDate 2005
dc.date.none.fl_str_mv 2005-05
2005-05-01T00:00:00Z
2019-04-09T10:27:26Z
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dc.type.driver.fl_str_mv info:eu-repo/semantics/article
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status_str publishedVersion
dc.identifier.uri.fl_str_mv http://hdl.handle.net/10400.22/13486
url http://hdl.handle.net/10400.22/13486
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv 1790-0832
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
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dc.source.none.fl_str_mv reponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
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repository.name.fl_str_mv Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
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