Automatic implementation of a re-configurable logic over ASIC design flow
Autor(a) principal: | |
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Data de Publicação: | 2017 |
Tipo de documento: | Dissertação |
Idioma: | eng |
Título da fonte: | Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
Texto Completo: | https://repositorio-aberto.up.pt/handle/10216/105356 |
Resumo: | The available density and complexity on Integrated Circuits (IC) has been increasing, following the improvement of technologies to design and fabric ICs leading to a challenging evolution, in the complexity of digital ICs on SoC design, to the semiconductor industry. As so extensive validation prior to fabrication as become increasingly demanding to ensure design correctness of the produced circuit.At the same time, with the current demand for faster turnaround development cycles, major interoperability tests are already performed in actual silicon, as errors can result on testing , the disposal of the produced chip and the need to create a new production cycle results in time and resources wasting. One of the clear solutions to this problem is the replacement of the original fixed logic with a reprogrammable one.This type of architecture can empower the designer the ability to perform minor updates, on site, changing minor errors and adding some needed, minor, functionalities.The main objective of the thesis, is to study and develop a generic configurable hardware structure, and create a new design flow that can be integrated into the normal work of the IC developer, that can be used in multiple projects and technologies, to create an adaptable architecture suitable to different implementations. |
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Automatic implementation of a re-configurable logic over ASIC design flowEngenharia electrotécnica, electrónica e informáticaElectrical engineering, Electronic engineering, Information engineeringThe available density and complexity on Integrated Circuits (IC) has been increasing, following the improvement of technologies to design and fabric ICs leading to a challenging evolution, in the complexity of digital ICs on SoC design, to the semiconductor industry. As so extensive validation prior to fabrication as become increasingly demanding to ensure design correctness of the produced circuit.At the same time, with the current demand for faster turnaround development cycles, major interoperability tests are already performed in actual silicon, as errors can result on testing , the disposal of the produced chip and the need to create a new production cycle results in time and resources wasting. One of the clear solutions to this problem is the replacement of the original fixed logic with a reprogrammable one.This type of architecture can empower the designer the ability to perform minor updates, on site, changing minor errors and adding some needed, minor, functionalities.The main objective of the thesis, is to study and develop a generic configurable hardware structure, and create a new design flow that can be integrated into the normal work of the IC developer, that can be used in multiple projects and technologies, to create an adaptable architecture suitable to different implementations.2017-07-042017-07-04T00:00:00Zinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/masterThesisapplication/pdfhttps://repositorio-aberto.up.pt/handle/10216/105356TID:201799812engJosé Delfim Ribeiro Valverdeinfo:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2023-11-29T13:17:31Zoai:repositorio-aberto.up.pt:10216/105356Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireopendoar:71602024-03-19T23:37:41.119581Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse |
dc.title.none.fl_str_mv |
Automatic implementation of a re-configurable logic over ASIC design flow |
title |
Automatic implementation of a re-configurable logic over ASIC design flow |
spellingShingle |
Automatic implementation of a re-configurable logic over ASIC design flow José Delfim Ribeiro Valverde Engenharia electrotécnica, electrónica e informática Electrical engineering, Electronic engineering, Information engineering |
title_short |
Automatic implementation of a re-configurable logic over ASIC design flow |
title_full |
Automatic implementation of a re-configurable logic over ASIC design flow |
title_fullStr |
Automatic implementation of a re-configurable logic over ASIC design flow |
title_full_unstemmed |
Automatic implementation of a re-configurable logic over ASIC design flow |
title_sort |
Automatic implementation of a re-configurable logic over ASIC design flow |
author |
José Delfim Ribeiro Valverde |
author_facet |
José Delfim Ribeiro Valverde |
author_role |
author |
dc.contributor.author.fl_str_mv |
José Delfim Ribeiro Valverde |
dc.subject.por.fl_str_mv |
Engenharia electrotécnica, electrónica e informática Electrical engineering, Electronic engineering, Information engineering |
topic |
Engenharia electrotécnica, electrónica e informática Electrical engineering, Electronic engineering, Information engineering |
description |
The available density and complexity on Integrated Circuits (IC) has been increasing, following the improvement of technologies to design and fabric ICs leading to a challenging evolution, in the complexity of digital ICs on SoC design, to the semiconductor industry. As so extensive validation prior to fabrication as become increasingly demanding to ensure design correctness of the produced circuit.At the same time, with the current demand for faster turnaround development cycles, major interoperability tests are already performed in actual silicon, as errors can result on testing , the disposal of the produced chip and the need to create a new production cycle results in time and resources wasting. One of the clear solutions to this problem is the replacement of the original fixed logic with a reprogrammable one.This type of architecture can empower the designer the ability to perform minor updates, on site, changing minor errors and adding some needed, minor, functionalities.The main objective of the thesis, is to study and develop a generic configurable hardware structure, and create a new design flow that can be integrated into the normal work of the IC developer, that can be used in multiple projects and technologies, to create an adaptable architecture suitable to different implementations. |
publishDate |
2017 |
dc.date.none.fl_str_mv |
2017-07-04 2017-07-04T00:00:00Z |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/masterThesis |
format |
masterThesis |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
https://repositorio-aberto.up.pt/handle/10216/105356 TID:201799812 |
url |
https://repositorio-aberto.up.pt/handle/10216/105356 |
identifier_str_mv |
TID:201799812 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.format.none.fl_str_mv |
application/pdf |
dc.source.none.fl_str_mv |
reponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação instacron:RCAAP |
instname_str |
Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação |
instacron_str |
RCAAP |
institution |
RCAAP |
reponame_str |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
collection |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
repository.name.fl_str_mv |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação |
repository.mail.fl_str_mv |
|
_version_ |
1799135690194157568 |