Cache-aware Schedulability Analysis of PREM Compliant Tasks

Detalhes bibliográficos
Autor(a) principal: Rashid, Syed Aftab
Data de Publicação: 2022
Outros Autores: Awan, Muhammad Ali, Souto, Pedro, Bletsas, Konstantinos, Tovar, Eduardo
Tipo de documento: Artigo
Idioma: eng
Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
Texto Completo: http://hdl.handle.net/10400.22/20900
Resumo: The Predictable Execution Model (PREM) is useful for mitigating inter-core interference due to shared resources such as the main memory. However, it is cache-agnostic, which makes schedulabulity analysis pessimistic, via overestimation of prefetches and write-backs. In response, we present cache-aware schedulability analysis for PREM tasks on fixed-task-priority partitioned multicores, that bounds the number of cache prefetches and write-backs. Our approach identifies memory blocks loaded in the execution of a previous scheduling interval of each task, that remain in the cache until its next scheduling interval. Doing so, greatly reduces the estimated prefetches and write backs. In experimental evaluations, our analysis improves the schedulability of PREM tasks by up to 55 percentage points.
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spelling Cache-aware Schedulability Analysis of PREM Compliant Tasks220101The Predictable Execution Model (PREM) is useful for mitigating inter-core interference due to shared resources such as the main memory. However, it is cache-agnostic, which makes schedulabulity analysis pessimistic, via overestimation of prefetches and write-backs. In response, we present cache-aware schedulability analysis for PREM tasks on fixed-task-priority partitioned multicores, that bounds the number of cache prefetches and write-backs. Our approach identifies memory blocks loaded in the execution of a previous scheduling interval of each task, that remain in the cache until its next scheduling interval. Doing so, greatly reduces the estimated prefetches and write backs. In experimental evaluations, our analysis improves the schedulability of PREM tasks by up to 55 percentage points.This work was partially supported by National Funds through FCT/MCTES (Portuguese Foundation for Science and Technology), within the CISTER Research Unit (UIDP/UIDB/04234/2020); also by the Operational Competitiveness Programme and Internationalization (COMPETE 2020) under the PT2020 Partnership Agreement, through the European Regional Development Fund (ERDF), and by national funds through the FCT, within project PREFECT (POCI-01-0145-FEDER-029119); also by the European Union’s Horizon 2020 - The EU Framework Programme for Research and Innovation 2014-2020, under grant agreement No. 732505. Project ”TEC4Growth - Pervasive Intelligence, Enhancers and Proofs of Concept with Industrial Impact/NORTE-01-0145- FEDER000020” financed by the North Portugal Regional Operational Programme (NORTE 2020), under the PORTUGAL 2020 Partnership AgreementIEEERepositório Científico do Instituto Politécnico do PortoRashid, Syed AftabAwan, Muhammad AliSouto, PedroBletsas, KonstantinosTovar, Eduardo2022-10-03T10:39:17Z2022-01-112022-01-11T00:00:00Zinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfhttp://hdl.handle.net/10400.22/20900eng10.23919/DATE54114.2022.9774670info:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2023-03-13T13:16:27Zoai:recipp.ipp.pt:10400.22/20900Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireopendoar:71602024-03-19T17:40:59.256350Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse
dc.title.none.fl_str_mv Cache-aware Schedulability Analysis of PREM Compliant Tasks
220101
title Cache-aware Schedulability Analysis of PREM Compliant Tasks
spellingShingle Cache-aware Schedulability Analysis of PREM Compliant Tasks
Rashid, Syed Aftab
title_short Cache-aware Schedulability Analysis of PREM Compliant Tasks
title_full Cache-aware Schedulability Analysis of PREM Compliant Tasks
title_fullStr Cache-aware Schedulability Analysis of PREM Compliant Tasks
title_full_unstemmed Cache-aware Schedulability Analysis of PREM Compliant Tasks
title_sort Cache-aware Schedulability Analysis of PREM Compliant Tasks
author Rashid, Syed Aftab
author_facet Rashid, Syed Aftab
Awan, Muhammad Ali
Souto, Pedro
Bletsas, Konstantinos
Tovar, Eduardo
author_role author
author2 Awan, Muhammad Ali
Souto, Pedro
Bletsas, Konstantinos
Tovar, Eduardo
author2_role author
author
author
author
dc.contributor.none.fl_str_mv Repositório Científico do Instituto Politécnico do Porto
dc.contributor.author.fl_str_mv Rashid, Syed Aftab
Awan, Muhammad Ali
Souto, Pedro
Bletsas, Konstantinos
Tovar, Eduardo
description The Predictable Execution Model (PREM) is useful for mitigating inter-core interference due to shared resources such as the main memory. However, it is cache-agnostic, which makes schedulabulity analysis pessimistic, via overestimation of prefetches and write-backs. In response, we present cache-aware schedulability analysis for PREM tasks on fixed-task-priority partitioned multicores, that bounds the number of cache prefetches and write-backs. Our approach identifies memory blocks loaded in the execution of a previous scheduling interval of each task, that remain in the cache until its next scheduling interval. Doing so, greatly reduces the estimated prefetches and write backs. In experimental evaluations, our analysis improves the schedulability of PREM tasks by up to 55 percentage points.
publishDate 2022
dc.date.none.fl_str_mv 2022-10-03T10:39:17Z
2022-01-11
2022-01-11T00:00:00Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/article
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dc.identifier.uri.fl_str_mv http://hdl.handle.net/10400.22/20900
url http://hdl.handle.net/10400.22/20900
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv 10.23919/DATE54114.2022.9774670
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dc.publisher.none.fl_str_mv IEEE
publisher.none.fl_str_mv IEEE
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