An integrated folded-patch chip-size antenna using high-resistivity polycrystalline silicon substrate
Autor(a) principal: | |
---|---|
Data de Publicação: | 2004 |
Outros Autores: | , , , |
Idioma: | eng |
Título da fonte: | Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
Texto Completo: | http://hdl.handle.net/1822/1619 |
Resumo: | High-resistivity polycrystalline silicon (HRPS) wafers are utilized as low-loss substrates for three-dimensional integration of on-chip antennas in wafer-level chip-scale packages (WLCSP). Sandwiching of HRPS and silicon wafers enables to integrate complex RF passives with a spacing of >150 µm to the conductive silicon substrate containing the circuitry, while providing mechanical stability, reducing form factor and avoiding any additional RF loss. A folded-patch antenna with dimensions of 2.5x2.5x1 mm3, operating at 5.7 GHz was analysed considering a 10 kΩ-cm HRPS wafer. The antenna has a –10 dB return loss bandwidth of 50 MHz and an efficiency of 58 %, a performance comparable to glass substrates. |
id |
RCAP_b6ec6cfc3e217b593176e9fede6b2027 |
---|---|
oai_identifier_str |
oai:repositorium.sdum.uminho.pt:1822/1619 |
network_acronym_str |
RCAP |
network_name_str |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
repository_id_str |
7160 |
spelling |
An integrated folded-patch chip-size antenna using high-resistivity polycrystalline silicon substrateIntegrated antennaFolded antennaSmall antennaWireless microsystemScience & TechnologyHigh-resistivity polycrystalline silicon (HRPS) wafers are utilized as low-loss substrates for three-dimensional integration of on-chip antennas in wafer-level chip-scale packages (WLCSP). Sandwiching of HRPS and silicon wafers enables to integrate complex RF passives with a spacing of >150 µm to the conductive silicon substrate containing the circuitry, while providing mechanical stability, reducing form factor and avoiding any additional RF loss. A folded-patch antenna with dimensions of 2.5x2.5x1 mm3, operating at 5.7 GHz was analysed considering a 10 kΩ-cm HRPS wafer. The antenna has a –10 dB return loss bandwidth of 50 MHz and an efficiency of 58 %, a performance comparable to glass substrates.Fundação Para a Ciência e Tecnologia (FCT) (SFRH/BD/4717/2001, POCTI/ESE/38468/2001, FEDER).IEEEUniversidade do MinhoMendes, P. M.Polyakov, A.Bartek, M.Burghartz, J. N.Correia, J. H.2004-102004-10-01T00:00:00Zconference paperinfo:eu-repo/semantics/publishedVersionapplication/pdfhttp://hdl.handle.net/1822/1619engASDAM. INTERNATIONAL CONFERENCE ON ADVANCED SEMICONDUCTOR DEVICES AND MICROSYSTEMS, 5, Smolenice Castle, 2004 - "Proceedings". Piscataway : IEEE, 2004. ISBN 0-7803-8535-7. p. 311-314.0-7803-8535-7info:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2024-05-11T05:02:12Zoai:repositorium.sdum.uminho.pt:1822/1619Portal AgregadorONGhttps://www.rcaap.pt/oai/openairemluisa.alvim@gmail.comopendoar:71602024-05-11T05:02:12Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse |
dc.title.none.fl_str_mv |
An integrated folded-patch chip-size antenna using high-resistivity polycrystalline silicon substrate |
title |
An integrated folded-patch chip-size antenna using high-resistivity polycrystalline silicon substrate |
spellingShingle |
An integrated folded-patch chip-size antenna using high-resistivity polycrystalline silicon substrate Mendes, P. M. Integrated antenna Folded antenna Small antenna Wireless microsystem Science & Technology |
title_short |
An integrated folded-patch chip-size antenna using high-resistivity polycrystalline silicon substrate |
title_full |
An integrated folded-patch chip-size antenna using high-resistivity polycrystalline silicon substrate |
title_fullStr |
An integrated folded-patch chip-size antenna using high-resistivity polycrystalline silicon substrate |
title_full_unstemmed |
An integrated folded-patch chip-size antenna using high-resistivity polycrystalline silicon substrate |
title_sort |
An integrated folded-patch chip-size antenna using high-resistivity polycrystalline silicon substrate |
author |
Mendes, P. M. |
author_facet |
Mendes, P. M. Polyakov, A. Bartek, M. Burghartz, J. N. Correia, J. H. |
author_role |
author |
author2 |
Polyakov, A. Bartek, M. Burghartz, J. N. Correia, J. H. |
author2_role |
author author author author |
dc.contributor.none.fl_str_mv |
Universidade do Minho |
dc.contributor.author.fl_str_mv |
Mendes, P. M. Polyakov, A. Bartek, M. Burghartz, J. N. Correia, J. H. |
dc.subject.por.fl_str_mv |
Integrated antenna Folded antenna Small antenna Wireless microsystem Science & Technology |
topic |
Integrated antenna Folded antenna Small antenna Wireless microsystem Science & Technology |
description |
High-resistivity polycrystalline silicon (HRPS) wafers are utilized as low-loss substrates for three-dimensional integration of on-chip antennas in wafer-level chip-scale packages (WLCSP). Sandwiching of HRPS and silicon wafers enables to integrate complex RF passives with a spacing of >150 µm to the conductive silicon substrate containing the circuitry, while providing mechanical stability, reducing form factor and avoiding any additional RF loss. A folded-patch antenna with dimensions of 2.5x2.5x1 mm3, operating at 5.7 GHz was analysed considering a 10 kΩ-cm HRPS wafer. The antenna has a –10 dB return loss bandwidth of 50 MHz and an efficiency of 58 %, a performance comparable to glass substrates. |
publishDate |
2004 |
dc.date.none.fl_str_mv |
2004-10 2004-10-01T00:00:00Z |
dc.type.driver.fl_str_mv |
conference paper |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://hdl.handle.net/1822/1619 |
url |
http://hdl.handle.net/1822/1619 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.none.fl_str_mv |
ASDAM. INTERNATIONAL CONFERENCE ON ADVANCED SEMICONDUCTOR DEVICES AND MICROSYSTEMS, 5, Smolenice Castle, 2004 - "Proceedings". Piscataway : IEEE, 2004. ISBN 0-7803-8535-7. p. 311-314. 0-7803-8535-7 |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.format.none.fl_str_mv |
application/pdf |
dc.publisher.none.fl_str_mv |
IEEE |
publisher.none.fl_str_mv |
IEEE |
dc.source.none.fl_str_mv |
reponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação instacron:RCAAP |
instname_str |
Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação |
instacron_str |
RCAAP |
institution |
RCAAP |
reponame_str |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
collection |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
repository.name.fl_str_mv |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação |
repository.mail.fl_str_mv |
mluisa.alvim@gmail.com |
_version_ |
1817544497747197952 |