Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs

Detalhes bibliográficos
Autor(a) principal: Dias, Tiago
Data de Publicação: 2014
Outros Autores: Roma, Nuno, Sousa, Leonel
Tipo de documento: Artigo
Idioma: eng
Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
Texto Completo: http://hdl.handle.net/10400.21/4844
Resumo: A unified architecture for fast and efficient computation of the set of two-dimensional (2-D) transforms adopted by the most recent state-of-the-art digital video standards is presented in this paper. Contrasting to other designs with similar functionality, the presented architecture is supported on a scalable, modular and completely configurable processing structure. This flexible structure not only allows to easily reconfigure the architecture to support different transform kernels, but it also permits its resizing to efficiently support transforms of different orders (e. g. order-4, order-8, order-16 and order-32). Consequently, not only is it highly suitable to realize high-performance multi-standard transform cores, but it also offers highly efficient implementations of specialized processing structures addressing only a reduced subset of transforms that are used by a specific video standard. The experimental results that were obtained by prototyping several configurations of this processing structure in a Xilinx Virtex-7 FPGA show the superior performance and hardware efficiency levels provided by the proposed unified architecture for the implementation of transform cores for the Advanced Video Coding (AVC), Audio Video coding Standard (AVS), VC-1 and High Efficiency Video Coding (HEVC) standards. In addition, such results also demonstrate the ability of this processing structure to realize multi-standard transform cores supporting all the standards mentioned above and that are capable of processing the 8k Ultra High Definition Television (UHDTV) video format (7,680 x 4,320 at 30 fps) in real time.
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spelling Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecsVideo CodingMulti-StandardTransform ArchitectureSystolic ArrayFPGAA unified architecture for fast and efficient computation of the set of two-dimensional (2-D) transforms adopted by the most recent state-of-the-art digital video standards is presented in this paper. Contrasting to other designs with similar functionality, the presented architecture is supported on a scalable, modular and completely configurable processing structure. This flexible structure not only allows to easily reconfigure the architecture to support different transform kernels, but it also permits its resizing to efficiently support transforms of different orders (e. g. order-4, order-8, order-16 and order-32). Consequently, not only is it highly suitable to realize high-performance multi-standard transform cores, but it also offers highly efficient implementations of specialized processing structures addressing only a reduced subset of transforms that are used by a specific video standard. The experimental results that were obtained by prototyping several configurations of this processing structure in a Xilinx Virtex-7 FPGA show the superior performance and hardware efficiency levels provided by the proposed unified architecture for the implementation of transform cores for the Advanced Video Coding (AVC), Audio Video coding Standard (AVS), VC-1 and High Efficiency Video Coding (HEVC) standards. In addition, such results also demonstrate the ability of this processing structure to realize multi-standard transform cores supporting all the standards mentioned above and that are capable of processing the 8k Ultra High Definition Television (UHDTV) video format (7,680 x 4,320 at 30 fps) in real time.Springer International Publishing AGRCIPLDias, TiagoRoma, NunoSousa, Leonel2015-08-19T10:14:36Z2014-072014-07-01T00:00:00Zinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfhttp://hdl.handle.net/10400.21/4844engDIAS, Tiago Miguel Braga da Silva; ROMA, Nuno; SOUSA, Leonel – Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs. Eurasip Journal on Advances in Signal Processing. ISSN: 1687-6180. (2014), Art. nr. 108.1687-6180metadata only accessinfo:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2023-08-03T09:47:25Zoai:repositorio.ipl.pt:10400.21/4844Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireopendoar:71602024-03-19T20:14:13.014738Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse
dc.title.none.fl_str_mv Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs
title Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs
spellingShingle Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs
Dias, Tiago
Video Coding
Multi-Standard
Transform Architecture
Systolic Array
FPGA
title_short Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs
title_full Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs
title_fullStr Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs
title_full_unstemmed Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs
title_sort Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs
author Dias, Tiago
author_facet Dias, Tiago
Roma, Nuno
Sousa, Leonel
author_role author
author2 Roma, Nuno
Sousa, Leonel
author2_role author
author
dc.contributor.none.fl_str_mv RCIPL
dc.contributor.author.fl_str_mv Dias, Tiago
Roma, Nuno
Sousa, Leonel
dc.subject.por.fl_str_mv Video Coding
Multi-Standard
Transform Architecture
Systolic Array
FPGA
topic Video Coding
Multi-Standard
Transform Architecture
Systolic Array
FPGA
description A unified architecture for fast and efficient computation of the set of two-dimensional (2-D) transforms adopted by the most recent state-of-the-art digital video standards is presented in this paper. Contrasting to other designs with similar functionality, the presented architecture is supported on a scalable, modular and completely configurable processing structure. This flexible structure not only allows to easily reconfigure the architecture to support different transform kernels, but it also permits its resizing to efficiently support transforms of different orders (e. g. order-4, order-8, order-16 and order-32). Consequently, not only is it highly suitable to realize high-performance multi-standard transform cores, but it also offers highly efficient implementations of specialized processing structures addressing only a reduced subset of transforms that are used by a specific video standard. The experimental results that were obtained by prototyping several configurations of this processing structure in a Xilinx Virtex-7 FPGA show the superior performance and hardware efficiency levels provided by the proposed unified architecture for the implementation of transform cores for the Advanced Video Coding (AVC), Audio Video coding Standard (AVS), VC-1 and High Efficiency Video Coding (HEVC) standards. In addition, such results also demonstrate the ability of this processing structure to realize multi-standard transform cores supporting all the standards mentioned above and that are capable of processing the 8k Ultra High Definition Television (UHDTV) video format (7,680 x 4,320 at 30 fps) in real time.
publishDate 2014
dc.date.none.fl_str_mv 2014-07
2014-07-01T00:00:00Z
2015-08-19T10:14:36Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/article
format article
status_str publishedVersion
dc.identifier.uri.fl_str_mv http://hdl.handle.net/10400.21/4844
url http://hdl.handle.net/10400.21/4844
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv DIAS, Tiago Miguel Braga da Silva; ROMA, Nuno; SOUSA, Leonel – Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs. Eurasip Journal on Advances in Signal Processing. ISSN: 1687-6180. (2014), Art. nr. 108.
1687-6180
dc.rights.driver.fl_str_mv metadata only access
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rights_invalid_str_mv metadata only access
eu_rights_str_mv openAccess
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dc.publisher.none.fl_str_mv Springer International Publishing AG
publisher.none.fl_str_mv Springer International Publishing AG
dc.source.none.fl_str_mv reponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
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instname_str Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
instacron_str RCAAP
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reponame_str Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
collection Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
repository.name.fl_str_mv Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
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