Response time analysis of COTS-Based multicores considering the contention on the shared memory bus
Autor(a) principal: | |
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Data de Publicação: | 2011 |
Outros Autores: | , , , , |
Tipo de documento: | Artigo |
Idioma: | eng |
Título da fonte: | Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
Texto Completo: | http://hdl.handle.net/10400.22/3740 |
Resumo: | The current industry trend is towards using Commercially available Off-The-Shelf (COTS) based multicores for developing real time embedded systems, as opposed to the usage of custom-made hardware. In typical implementation of such COTS-based multicores, multiple cores access the main memory via a shared bus. This often leads to contention on this shared channel, which results in an increase of the response time of the tasks. Analyzing this increased response time, considering the contention on the shared bus, is challenging on COTS-based systems mainly because bus arbitration protocols are often undocumented and the exact instants at which the shared bus is accessed by tasks are not explicitly controlled by the operating system scheduler; they are instead a result of cache misses. This paper makes three contributions towards analyzing tasks scheduled on COTS-based multicores. Firstly, we describe a method to model the memory access patterns of a task. Secondly, we apply this model to analyze the worst case response time for a set of tasks. Although the required parameters to obtain the request profile can be obtained by static analysis, we provide an alternative method to experimentally obtain them by using performance monitoring counters (PMCs). We also compare our work against an existing approach and show that our approach outperforms it by providing tighter upper-bound on the number of bus requests generated by a task. |
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Response time analysis of COTS-Based multicores considering the contention on the shared memory busThe current industry trend is towards using Commercially available Off-The-Shelf (COTS) based multicores for developing real time embedded systems, as opposed to the usage of custom-made hardware. In typical implementation of such COTS-based multicores, multiple cores access the main memory via a shared bus. This often leads to contention on this shared channel, which results in an increase of the response time of the tasks. Analyzing this increased response time, considering the contention on the shared bus, is challenging on COTS-based systems mainly because bus arbitration protocols are often undocumented and the exact instants at which the shared bus is accessed by tasks are not explicitly controlled by the operating system scheduler; they are instead a result of cache misses. This paper makes three contributions towards analyzing tasks scheduled on COTS-based multicores. Firstly, we describe a method to model the memory access patterns of a task. Secondly, we apply this model to analyze the worst case response time for a set of tasks. Although the required parameters to obtain the request profile can be obtained by static analysis, we provide an alternative method to experimentally obtain them by using performance monitoring counters (PMCs). We also compare our work against an existing approach and show that our approach outperforms it by providing tighter upper-bound on the number of bus requests generated by a task.IEEERepositório Científico do Instituto Politécnico do PortoDasari, DakshinaAndersson, BjörnNélis, VincentPetters, Stefan M.Easwaran, ArvindLee, Jinkyu2014-02-06T14:55:27Z20112011-01-01T00:00:00Zinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfhttp://hdl.handle.net/10400.22/3740eng978-1-4577-2135-910.1109/TrustCom.2011.146metadata only accessinfo:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2023-03-13T12:43:35Zoai:recipp.ipp.pt:10400.22/3740Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireopendoar:71602024-03-19T17:24:45.000144Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse |
dc.title.none.fl_str_mv |
Response time analysis of COTS-Based multicores considering the contention on the shared memory bus |
title |
Response time analysis of COTS-Based multicores considering the contention on the shared memory bus |
spellingShingle |
Response time analysis of COTS-Based multicores considering the contention on the shared memory bus Dasari, Dakshina |
title_short |
Response time analysis of COTS-Based multicores considering the contention on the shared memory bus |
title_full |
Response time analysis of COTS-Based multicores considering the contention on the shared memory bus |
title_fullStr |
Response time analysis of COTS-Based multicores considering the contention on the shared memory bus |
title_full_unstemmed |
Response time analysis of COTS-Based multicores considering the contention on the shared memory bus |
title_sort |
Response time analysis of COTS-Based multicores considering the contention on the shared memory bus |
author |
Dasari, Dakshina |
author_facet |
Dasari, Dakshina Andersson, Björn Nélis, Vincent Petters, Stefan M. Easwaran, Arvind Lee, Jinkyu |
author_role |
author |
author2 |
Andersson, Björn Nélis, Vincent Petters, Stefan M. Easwaran, Arvind Lee, Jinkyu |
author2_role |
author author author author author |
dc.contributor.none.fl_str_mv |
Repositório Científico do Instituto Politécnico do Porto |
dc.contributor.author.fl_str_mv |
Dasari, Dakshina Andersson, Björn Nélis, Vincent Petters, Stefan M. Easwaran, Arvind Lee, Jinkyu |
description |
The current industry trend is towards using Commercially available Off-The-Shelf (COTS) based multicores for developing real time embedded systems, as opposed to the usage of custom-made hardware. In typical implementation of such COTS-based multicores, multiple cores access the main memory via a shared bus. This often leads to contention on this shared channel, which results in an increase of the response time of the tasks. Analyzing this increased response time, considering the contention on the shared bus, is challenging on COTS-based systems mainly because bus arbitration protocols are often undocumented and the exact instants at which the shared bus is accessed by tasks are not explicitly controlled by the operating system scheduler; they are instead a result of cache misses. This paper makes three contributions towards analyzing tasks scheduled on COTS-based multicores. Firstly, we describe a method to model the memory access patterns of a task. Secondly, we apply this model to analyze the worst case response time for a set of tasks. Although the required parameters to obtain the request profile can be obtained by static analysis, we provide an alternative method to experimentally obtain them by using performance monitoring counters (PMCs). We also compare our work against an existing approach and show that our approach outperforms it by providing tighter upper-bound on the number of bus requests generated by a task. |
publishDate |
2011 |
dc.date.none.fl_str_mv |
2011 2011-01-01T00:00:00Z 2014-02-06T14:55:27Z |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/article |
format |
article |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://hdl.handle.net/10400.22/3740 |
url |
http://hdl.handle.net/10400.22/3740 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.none.fl_str_mv |
978-1-4577-2135-9 10.1109/TrustCom.2011.146 |
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metadata only access info:eu-repo/semantics/openAccess |
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metadata only access |
eu_rights_str_mv |
openAccess |
dc.format.none.fl_str_mv |
application/pdf |
dc.publisher.none.fl_str_mv |
IEEE |
publisher.none.fl_str_mv |
IEEE |
dc.source.none.fl_str_mv |
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Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação |
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RCAAP |
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RCAAP |
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Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
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Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
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Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação |
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