Study of a Calibration Scheme for a Sigma-Delta Modulator Using Passive Integrators

Detalhes bibliográficos
Autor(a) principal: Brito, Inês Ferreira Casaleiro Nogueira de
Data de Publicação: 2023
Tipo de documento: Dissertação
Idioma: eng
Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
Texto Completo: http://hdl.handle.net/10362/173160
Resumo: In modern electronics systems there has been a great push to have a constant size re- duction of Complementary Metal-Oxide-Semiconductor (CMOS) technologies which can have different consequences, such as a reduction of the intrinsic gain of CMOS transistors and an increase of their transition frequency. This has resulted in increasing the difficulty of designing high gain, high bandwidth low power amplifiers. This can be a problem when designing high performance Sigma-Delta Modulators (Σ∆Ms). Recently, it was pro- posed to use active-passive Σ∆Ms architectures, where the loop gain is mainly obtained from the comparators processing gain, thus reducing the gain required for the amplifiers. Multi-stAge Noise SHaping (MASH) structures present a stable alternative to high-order single-loop typologies. Nevertheless, typically, these are very sensitive to the analog cir- cuit imperfections, since their performance relies on the accuracy of the values of the analog circuit’s transfer functions matching with the coefficients in the Digital Cancella- tion Logic (DCL) in order to avoid noise leakage and achieve their desired performance. This is the case with the passive 2-1 MASH Σ∆M developed based on [1], which has it’s performance limited by process variations of the values of it’s constituted components. In the used CMOS technology, process variations can cause the R · C value to change up to 37%, which causes mismatch between the Σ∆M analog transfer functions and the DCL transfer functions and also causes a variation in the overloading voltage of the modulator. Both these issues can cause degradation in Signal-to-Noise-and-Distortion Ratio (SNDR) of the modulator. In order to solve these problems, this thesis proposes a circuit capable of measuring the value of RC TS and then using this value to calibrate the coefficients in the DCL to match the analog transfer functions and adjust the reference voltage (Vref ) in order to reduce the variation of the Σ∆M overload voltage. In order to validate the calibration concept, the performance of 2-1 MASH Σ∆M implemented with and without calibration was analyzed by performing process, voltage and temperature (PVT) corners and Monte Carlo simulations. The results show that by implementing the calibration it was possible to reduce the variability of the SNDR results, as well as increase worst corners results.
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spelling Study of a Calibration Scheme for a Sigma-Delta Modulator Using Passive IntegratorsAnalog to Digital Converter (ADC)Sigma-Delta Modulators (Σ∆Ms)2-1 MASH Σ∆MPassive IntegratorsRC Time Constant CalibrationRC Time ConstantDomínio/Área Científica::Engenharia e Tecnologia::Engenharia Eletrotécnica, Eletrónica e InformáticaIn modern electronics systems there has been a great push to have a constant size re- duction of Complementary Metal-Oxide-Semiconductor (CMOS) technologies which can have different consequences, such as a reduction of the intrinsic gain of CMOS transistors and an increase of their transition frequency. This has resulted in increasing the difficulty of designing high gain, high bandwidth low power amplifiers. This can be a problem when designing high performance Sigma-Delta Modulators (Σ∆Ms). Recently, it was pro- posed to use active-passive Σ∆Ms architectures, where the loop gain is mainly obtained from the comparators processing gain, thus reducing the gain required for the amplifiers. Multi-stAge Noise SHaping (MASH) structures present a stable alternative to high-order single-loop typologies. Nevertheless, typically, these are very sensitive to the analog cir- cuit imperfections, since their performance relies on the accuracy of the values of the analog circuit’s transfer functions matching with the coefficients in the Digital Cancella- tion Logic (DCL) in order to avoid noise leakage and achieve their desired performance. This is the case with the passive 2-1 MASH Σ∆M developed based on [1], which has it’s performance limited by process variations of the values of it’s constituted components. In the used CMOS technology, process variations can cause the R · C value to change up to 37%, which causes mismatch between the Σ∆M analog transfer functions and the DCL transfer functions and also causes a variation in the overloading voltage of the modulator. Both these issues can cause degradation in Signal-to-Noise-and-Distortion Ratio (SNDR) of the modulator. In order to solve these problems, this thesis proposes a circuit capable of measuring the value of RC TS and then using this value to calibrate the coefficients in the DCL to match the analog transfer functions and adjust the reference voltage (Vref ) in order to reduce the variation of the Σ∆M overload voltage. In order to validate the calibration concept, the performance of 2-1 MASH Σ∆M implemented with and without calibration was analyzed by performing process, voltage and temperature (PVT) corners and Monte Carlo simulations. The results show that by implementing the calibration it was possible to reduce the variability of the SNDR results, as well as increase worst corners results.Ao longo do tempo, a tecnologia CMOS tem evoluindo de forma a permitir a progressiva redução das dimensões dos transístores. Esta redução permitiu o aumento da frequência máxima de operação (frequência de transição) dos transístores, mas resultou também na redução do seu ganho intrínseco. Assim, desenvolver amplificadores de elevada largura de banda e ganho, com baixos níveis de potência dissipada tornou-se um grande desafio. O que pode representar um problema no desenvolvimento de Moduladores Sigma-Delta (Σ∆Ms) de alto desempenho. Recentemente, tem-se proposto a utilização de arquitetu- ras Σ∆ passivas ou híbridas activas-passivas, em que o ganho de malha do modulador depende, em grande parte, do ganho de processamento do comparador, evitando a neces- sidade de amplificadores de alto desempenho. O que é uma vantagem na implementação das estruturas em cascata (MASH), que, tipicamente, são mais sensíveis às imperfeições da parte analógica do circuito. Isto deve-se ao facto do seu desempenho estar altamente dependente da correspondência entre as funções de transferência do circuito analógico e os coeficientes registados na lógica de cancelamento digital (DCL). Este é o caso do mo- dulador Σ∆ desenvolvido com base na tese [1], que tem o seu desempenho limitado pelas variações de processo que afetam as suas componentes. Estas variações podem causar uma variação R·C máxima de 37%, provocando alterações no ganho do modulador e uma divergência entre os coeficientes analógicos (provenientes das funções de transferência do circuito) e digitais (DCL), o que resulta na degradação no desempenho do circuito. Assim, nesta tese propõe-se um método de calibração baseado num circuito capaz de medir a variação de RC TS , de forma a converter esta variação num coeficiente digital capaz de calibrar os coeficientes da DCL de forma a coincidirem com as funções de transferência analógicas e calibrar a tensão de referência do ADC, de modo a diminuir a variabilidade da sua realimentação. De forma a validar o proposto método de calibração, o modula- dor Σ∆ foi simulado com e sem calibração, tendo em conta as variações de processo, temperatura e diferença de potencial máximas e também de Monte Carlo. Estas simu- lações demonstraram a capacidade do circuito de calibração em reduzir a variabilidade dos resultados SNDR, tal como aumentar o desempenho do ADC, nas piores condições.Paulino, NunoNowacki, BlazejRUNBrito, Inês Ferreira Casaleiro Nogueira de2024-10-08T13:27:28Z2023-042023-04-01T00:00:00Zinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/masterThesisapplication/pdfhttp://hdl.handle.net/10362/173160enginfo:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2024-10-14T01:38:55Zoai:run.unl.pt:10362/173160Portal AgregadorONGhttps://www.rcaap.pt/oai/openairemluisa.alvim@gmail.comopendoar:71602024-10-14T01:38:55Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse
dc.title.none.fl_str_mv Study of a Calibration Scheme for a Sigma-Delta Modulator Using Passive Integrators
title Study of a Calibration Scheme for a Sigma-Delta Modulator Using Passive Integrators
spellingShingle Study of a Calibration Scheme for a Sigma-Delta Modulator Using Passive Integrators
Brito, Inês Ferreira Casaleiro Nogueira de
Analog to Digital Converter (ADC)
Sigma-Delta Modulators (Σ∆Ms)
2-1 MASH Σ∆M
Passive Integrators
RC Time Constant Calibration
RC Time Constant
Domínio/Área Científica::Engenharia e Tecnologia::Engenharia Eletrotécnica, Eletrónica e Informática
title_short Study of a Calibration Scheme for a Sigma-Delta Modulator Using Passive Integrators
title_full Study of a Calibration Scheme for a Sigma-Delta Modulator Using Passive Integrators
title_fullStr Study of a Calibration Scheme for a Sigma-Delta Modulator Using Passive Integrators
title_full_unstemmed Study of a Calibration Scheme for a Sigma-Delta Modulator Using Passive Integrators
title_sort Study of a Calibration Scheme for a Sigma-Delta Modulator Using Passive Integrators
author Brito, Inês Ferreira Casaleiro Nogueira de
author_facet Brito, Inês Ferreira Casaleiro Nogueira de
author_role author
dc.contributor.none.fl_str_mv Paulino, Nuno
Nowacki, Blazej
RUN
dc.contributor.author.fl_str_mv Brito, Inês Ferreira Casaleiro Nogueira de
dc.subject.por.fl_str_mv Analog to Digital Converter (ADC)
Sigma-Delta Modulators (Σ∆Ms)
2-1 MASH Σ∆M
Passive Integrators
RC Time Constant Calibration
RC Time Constant
Domínio/Área Científica::Engenharia e Tecnologia::Engenharia Eletrotécnica, Eletrónica e Informática
topic Analog to Digital Converter (ADC)
Sigma-Delta Modulators (Σ∆Ms)
2-1 MASH Σ∆M
Passive Integrators
RC Time Constant Calibration
RC Time Constant
Domínio/Área Científica::Engenharia e Tecnologia::Engenharia Eletrotécnica, Eletrónica e Informática
description In modern electronics systems there has been a great push to have a constant size re- duction of Complementary Metal-Oxide-Semiconductor (CMOS) technologies which can have different consequences, such as a reduction of the intrinsic gain of CMOS transistors and an increase of their transition frequency. This has resulted in increasing the difficulty of designing high gain, high bandwidth low power amplifiers. This can be a problem when designing high performance Sigma-Delta Modulators (Σ∆Ms). Recently, it was pro- posed to use active-passive Σ∆Ms architectures, where the loop gain is mainly obtained from the comparators processing gain, thus reducing the gain required for the amplifiers. Multi-stAge Noise SHaping (MASH) structures present a stable alternative to high-order single-loop typologies. Nevertheless, typically, these are very sensitive to the analog cir- cuit imperfections, since their performance relies on the accuracy of the values of the analog circuit’s transfer functions matching with the coefficients in the Digital Cancella- tion Logic (DCL) in order to avoid noise leakage and achieve their desired performance. This is the case with the passive 2-1 MASH Σ∆M developed based on [1], which has it’s performance limited by process variations of the values of it’s constituted components. In the used CMOS technology, process variations can cause the R · C value to change up to 37%, which causes mismatch between the Σ∆M analog transfer functions and the DCL transfer functions and also causes a variation in the overloading voltage of the modulator. Both these issues can cause degradation in Signal-to-Noise-and-Distortion Ratio (SNDR) of the modulator. In order to solve these problems, this thesis proposes a circuit capable of measuring the value of RC TS and then using this value to calibrate the coefficients in the DCL to match the analog transfer functions and adjust the reference voltage (Vref ) in order to reduce the variation of the Σ∆M overload voltage. In order to validate the calibration concept, the performance of 2-1 MASH Σ∆M implemented with and without calibration was analyzed by performing process, voltage and temperature (PVT) corners and Monte Carlo simulations. The results show that by implementing the calibration it was possible to reduce the variability of the SNDR results, as well as increase worst corners results.
publishDate 2023
dc.date.none.fl_str_mv 2023-04
2023-04-01T00:00:00Z
2024-10-08T13:27:28Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/masterThesis
format masterThesis
status_str publishedVersion
dc.identifier.uri.fl_str_mv http://hdl.handle.net/10362/173160
url http://hdl.handle.net/10362/173160
dc.language.iso.fl_str_mv eng
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instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
instacron:RCAAP
instname_str Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
instacron_str RCAAP
institution RCAAP
reponame_str Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
collection Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
repository.name.fl_str_mv Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
repository.mail.fl_str_mv mluisa.alvim@gmail.com
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