A modular architecture for BIST of boundary scan boards

Detalhes bibliográficos
Autor(a) principal: José M. M. Ferreira
Data de Publicação: 1992
Outros Autores: Filipe S. Pinto, José S. Matos
Tipo de documento: Livro
Idioma: eng
Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
Texto Completo: https://repositorio-aberto.up.pt/handle/10216/84586
Resumo: A board-level BIST architecture for boards loaded with ASICs and VLSI components, compliant with the IEEE 1149.1 BST standard, is described. This BIST architecture consists of a test processor core, with an optimized architecture for controlling the board-level BST (boundary scan test) infrastructure, an optional system-level testability bus interface, to be included when a system-level test strategy is to be implemented, and a ROM containing the test program, which is automatically generated by an ATPG tool.
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spelling A modular architecture for BIST of boundary scan boardsEngenharia electrotécnica, Engenharia electrotécnica, electrónica e informáticaElectrical engineering, Electrical engineering, Electronic engineering, Information engineeringA board-level BIST architecture for boards loaded with ASICs and VLSI components, compliant with the IEEE 1149.1 BST standard, is described. This BIST architecture consists of a test processor core, with an optimized architecture for controlling the board-level BST (boundary scan test) infrastructure, an optional system-level testability bus interface, to be included when a system-level test strategy is to be implemented, and a ROM containing the test program, which is automatically generated by an ATPG tool.19921992-01-01T00:00:00Zinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/bookapplication/pdfhttps://repositorio-aberto.up.pt/handle/10216/84586eng10.1109/EUASIC.1992.228027José M. M. FerreiraFilipe S. PintoJosé S. Matosinfo:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2023-11-29T15:03:10Zoai:repositorio-aberto.up.pt:10216/84586Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireopendoar:71602024-03-20T00:14:31.377758Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse
dc.title.none.fl_str_mv A modular architecture for BIST of boundary scan boards
title A modular architecture for BIST of boundary scan boards
spellingShingle A modular architecture for BIST of boundary scan boards
José M. M. Ferreira
Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
title_short A modular architecture for BIST of boundary scan boards
title_full A modular architecture for BIST of boundary scan boards
title_fullStr A modular architecture for BIST of boundary scan boards
title_full_unstemmed A modular architecture for BIST of boundary scan boards
title_sort A modular architecture for BIST of boundary scan boards
author José M. M. Ferreira
author_facet José M. M. Ferreira
Filipe S. Pinto
José S. Matos
author_role author
author2 Filipe S. Pinto
José S. Matos
author2_role author
author
dc.contributor.author.fl_str_mv José M. M. Ferreira
Filipe S. Pinto
José S. Matos
dc.subject.por.fl_str_mv Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
topic Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
description A board-level BIST architecture for boards loaded with ASICs and VLSI components, compliant with the IEEE 1149.1 BST standard, is described. This BIST architecture consists of a test processor core, with an optimized architecture for controlling the board-level BST (boundary scan test) infrastructure, an optional system-level testability bus interface, to be included when a system-level test strategy is to be implemented, and a ROM containing the test program, which is automatically generated by an ATPG tool.
publishDate 1992
dc.date.none.fl_str_mv 1992
1992-01-01T00:00:00Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/book
format book
status_str publishedVersion
dc.identifier.uri.fl_str_mv https://repositorio-aberto.up.pt/handle/10216/84586
url https://repositorio-aberto.up.pt/handle/10216/84586
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv 10.1109/EUASIC.1992.228027
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.source.none.fl_str_mv reponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
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instname_str Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
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collection Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
repository.name.fl_str_mv Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
repository.mail.fl_str_mv
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