A Survey on Programmable LDPC Decoders
Autor(a) principal: | |
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Data de Publicação: | 2016 |
Outros Autores: | , , |
Tipo de documento: | Artigo |
Idioma: | eng |
Título da fonte: | Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
Texto Completo: | http://hdl.handle.net/10316/102240 https://doi.org/10.1109/ACCESS.2016.2594265 |
Resumo: | Low-density parity-check (LDPC) block codes are popular forward error correction schemes due to their capacity-approaching characteristics. However, the realization of LDPC decoders that meet both low latency and high throughput is not a trivial challenge. Usually, this has been solved with the ASIC and FPGA technology that enables meeting the decoder design constraints. But the rise of parallel architectures, such as graphics processing units, and the scaling of CPU streaming extensions has shown that multicore and many-core technology can provide a flexible alternative to the development of dedicated LDPC decoders for the compute-intensive prototyping phase of the design of new codes. Under this light, this paper surveys the most relevant publications made in the past decade to programmable LDPC decoders. It looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features. This paper concludes with a set of open problems in the field of communication systems on parallel programmable and reconfigurable architectures. |
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A Survey on Programmable LDPC DecodersLDPC codesLDPC decodersparallel computingCPUGPUrecon gurable computinghigh-level synthesisLow-density parity-check (LDPC) block codes are popular forward error correction schemes due to their capacity-approaching characteristics. However, the realization of LDPC decoders that meet both low latency and high throughput is not a trivial challenge. Usually, this has been solved with the ASIC and FPGA technology that enables meeting the decoder design constraints. But the rise of parallel architectures, such as graphics processing units, and the scaling of CPU streaming extensions has shown that multicore and many-core technology can provide a flexible alternative to the development of dedicated LDPC decoders for the compute-intensive prototyping phase of the design of new codes. Under this light, this paper surveys the most relevant publications made in the past decade to programmable LDPC decoders. It looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features. This paper concludes with a set of open problems in the field of communication systems on parallel programmable and reconfigurable architectures.2016info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articlehttp://hdl.handle.net/10316/102240http://hdl.handle.net/10316/102240https://doi.org/10.1109/ACCESS.2016.2594265eng2169-3536Andrade, JoãoFalcão, GabrielSilva, VitorSousa, Leonelinfo:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2022-09-29T20:40:51Zoai:estudogeral.uc.pt:10316/102240Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireopendoar:71602024-03-19T21:19:16.619254Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse |
dc.title.none.fl_str_mv |
A Survey on Programmable LDPC Decoders |
title |
A Survey on Programmable LDPC Decoders |
spellingShingle |
A Survey on Programmable LDPC Decoders Andrade, João LDPC codes LDPC decoders parallel computing CPU GPU recon gurable computing high-level synthesis |
title_short |
A Survey on Programmable LDPC Decoders |
title_full |
A Survey on Programmable LDPC Decoders |
title_fullStr |
A Survey on Programmable LDPC Decoders |
title_full_unstemmed |
A Survey on Programmable LDPC Decoders |
title_sort |
A Survey on Programmable LDPC Decoders |
author |
Andrade, João |
author_facet |
Andrade, João Falcão, Gabriel Silva, Vitor Sousa, Leonel |
author_role |
author |
author2 |
Falcão, Gabriel Silva, Vitor Sousa, Leonel |
author2_role |
author author author |
dc.contributor.author.fl_str_mv |
Andrade, João Falcão, Gabriel Silva, Vitor Sousa, Leonel |
dc.subject.por.fl_str_mv |
LDPC codes LDPC decoders parallel computing CPU GPU recon gurable computing high-level synthesis |
topic |
LDPC codes LDPC decoders parallel computing CPU GPU recon gurable computing high-level synthesis |
description |
Low-density parity-check (LDPC) block codes are popular forward error correction schemes due to their capacity-approaching characteristics. However, the realization of LDPC decoders that meet both low latency and high throughput is not a trivial challenge. Usually, this has been solved with the ASIC and FPGA technology that enables meeting the decoder design constraints. But the rise of parallel architectures, such as graphics processing units, and the scaling of CPU streaming extensions has shown that multicore and many-core technology can provide a flexible alternative to the development of dedicated LDPC decoders for the compute-intensive prototyping phase of the design of new codes. Under this light, this paper surveys the most relevant publications made in the past decade to programmable LDPC decoders. It looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features. This paper concludes with a set of open problems in the field of communication systems on parallel programmable and reconfigurable architectures. |
publishDate |
2016 |
dc.date.none.fl_str_mv |
2016 |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/article |
format |
article |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://hdl.handle.net/10316/102240 http://hdl.handle.net/10316/102240 https://doi.org/10.1109/ACCESS.2016.2594265 |
url |
http://hdl.handle.net/10316/102240 https://doi.org/10.1109/ACCESS.2016.2594265 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.none.fl_str_mv |
2169-3536 |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.source.none.fl_str_mv |
reponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação instacron:RCAAP |
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Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação |
instacron_str |
RCAAP |
institution |
RCAAP |
reponame_str |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
collection |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
repository.name.fl_str_mv |
Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação |
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1799134087077691392 |