Decimal multiplication in FPGA with a novel decimal adder/subtractor
Autor(a) principal: | |
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Data de Publicação: | 2021 |
Outros Autores: | |
Tipo de documento: | Artigo |
Idioma: | eng |
Título da fonte: | Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
Texto Completo: | http://hdl.handle.net/10400.21/13833 |
Resumo: | Financial and commercial data are mostly represented in decimal format. To avoid errors introduced when converting some decimal fractions to binary, these data are processed with decimal arithmetic. Most processors only have hardwired binary arithmetic units. So, decimal operations are executed with slow software-based decimal arithmetic functions. For the fast execution of decimal operations, dedicated hardware units have been proposed and designed in FPGA. Decimal multiplication is found in most decimal-based applications and so its optimized design is very important for fast execution. In this paper two new parallel decimal multipliers in FPGA are proposed. These are based on a new decimal adder/subtractor also proposed in this paper. The new decimal multipliers improve state-of-the-art parallel decimal multipliers. Compared to previous architectures, implementation results show that the proposed multipliers achieve 26% better area and 12% better performance. Also, the new decimal multipliers reduce the area and performance gap to binary multipliers and are smaller for 32 digit operands. |
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Decimal multiplication in FPGA with a novel decimal adder/subtractorDecimal multiplicationDecimal adder parallel multiplicationExcess-3 codingFPGAFinancial and commercial data are mostly represented in decimal format. To avoid errors introduced when converting some decimal fractions to binary, these data are processed with decimal arithmetic. Most processors only have hardwired binary arithmetic units. So, decimal operations are executed with slow software-based decimal arithmetic functions. For the fast execution of decimal operations, dedicated hardware units have been proposed and designed in FPGA. Decimal multiplication is found in most decimal-based applications and so its optimized design is very important for fast execution. In this paper two new parallel decimal multipliers in FPGA are proposed. These are based on a new decimal adder/subtractor also proposed in this paper. The new decimal multipliers improve state-of-the-art parallel decimal multipliers. Compared to previous architectures, implementation results show that the proposed multipliers achieve 26% better area and 12% better performance. Also, the new decimal multipliers reduce the area and performance gap to binary multipliers and are smaller for 32 digit operands.MDPIRCIPLVéstias, MárioNeto, Horácio C2021-10-07T12:56:03Z2021-06-292021-06-29T00:00:00Zinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfhttp://hdl.handle.net/10400.21/13833engVÉSTIAS, Mário P.; NETO, Horácio C. – Decimal multiplication in FPGA with a novel decimal adder/subtractor. Algorithms. eISSN 1999-4893. Vol. 14, N.º 7 (2021), pp. 1-2110.3390/a140701981999-4893info:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2023-08-03T10:09:12Zoai:repositorio.ipl.pt:10400.21/13833Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireopendoar:71602024-03-19T20:21:42.737095Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse |
dc.title.none.fl_str_mv |
Decimal multiplication in FPGA with a novel decimal adder/subtractor |
title |
Decimal multiplication in FPGA with a novel decimal adder/subtractor |
spellingShingle |
Decimal multiplication in FPGA with a novel decimal adder/subtractor Véstias, Mário Decimal multiplication Decimal adder parallel multiplication Excess-3 coding FPGA |
title_short |
Decimal multiplication in FPGA with a novel decimal adder/subtractor |
title_full |
Decimal multiplication in FPGA with a novel decimal adder/subtractor |
title_fullStr |
Decimal multiplication in FPGA with a novel decimal adder/subtractor |
title_full_unstemmed |
Decimal multiplication in FPGA with a novel decimal adder/subtractor |
title_sort |
Decimal multiplication in FPGA with a novel decimal adder/subtractor |
author |
Véstias, Mário |
author_facet |
Véstias, Mário Neto, Horácio C |
author_role |
author |
author2 |
Neto, Horácio C |
author2_role |
author |
dc.contributor.none.fl_str_mv |
RCIPL |
dc.contributor.author.fl_str_mv |
Véstias, Mário Neto, Horácio C |
dc.subject.por.fl_str_mv |
Decimal multiplication Decimal adder parallel multiplication Excess-3 coding FPGA |
topic |
Decimal multiplication Decimal adder parallel multiplication Excess-3 coding FPGA |
description |
Financial and commercial data are mostly represented in decimal format. To avoid errors introduced when converting some decimal fractions to binary, these data are processed with decimal arithmetic. Most processors only have hardwired binary arithmetic units. So, decimal operations are executed with slow software-based decimal arithmetic functions. For the fast execution of decimal operations, dedicated hardware units have been proposed and designed in FPGA. Decimal multiplication is found in most decimal-based applications and so its optimized design is very important for fast execution. In this paper two new parallel decimal multipliers in FPGA are proposed. These are based on a new decimal adder/subtractor also proposed in this paper. The new decimal multipliers improve state-of-the-art parallel decimal multipliers. Compared to previous architectures, implementation results show that the proposed multipliers achieve 26% better area and 12% better performance. Also, the new decimal multipliers reduce the area and performance gap to binary multipliers and are smaller for 32 digit operands. |
publishDate |
2021 |
dc.date.none.fl_str_mv |
2021-10-07T12:56:03Z 2021-06-29 2021-06-29T00:00:00Z |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/article |
format |
article |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://hdl.handle.net/10400.21/13833 |
url |
http://hdl.handle.net/10400.21/13833 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.none.fl_str_mv |
VÉSTIAS, Mário P.; NETO, Horácio C. – Decimal multiplication in FPGA with a novel decimal adder/subtractor. Algorithms. eISSN 1999-4893. Vol. 14, N.º 7 (2021), pp. 1-21 10.3390/a14070198 1999-4893 |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.format.none.fl_str_mv |
application/pdf |
dc.publisher.none.fl_str_mv |
MDPI |
publisher.none.fl_str_mv |
MDPI |
dc.source.none.fl_str_mv |
reponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação instacron:RCAAP |
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Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação |
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RCAAP |
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RCAAP |
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Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
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Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) |
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Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação |
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1799133488929046528 |