Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems

Detalhes bibliográficos
Autor(a) principal: Miguel L. Silva
Data de Publicação: 2005
Outros Autores: João Canas Ferreira
Tipo de documento: Livro
Idioma: eng
Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
Texto Completo: https://hdl.handle.net/10216/70151
Resumo: This paper describes a tool that creates partially-reconfigurable modules from the bitstreams of individual component modules. The resulting modules are intended for use in applications that exploit partial dynamic reconfiguration. The tool is integrated in a design flow particularly aimed at dynamically-reconfigurable platform FPGAs. The corresponding design flow is described together with a basic run-time support system.
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spelling Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systemsEngenharia electrotécnica, Engenharia electrotécnica, electrónica e informáticaElectrical engineering, Electrical engineering, Electronic engineering, Information engineeringThis paper describes a tool that creates partially-reconfigurable modules from the bitstreams of individual component modules. The resulting modules are intended for use in applications that exploit partial dynamic reconfiguration. The tool is integrated in a design flow particularly aimed at dynamically-reconfigurable platform FPGAs. The corresponding design flow is described together with a basic run-time support system.20052005-01-01T00:00:00Zinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/bookapplication/pdfhttps://hdl.handle.net/10216/70151eng10.1049/iet-cdt:20060056Miguel L. SilvaJoão Canas Ferreirainfo:eu-repo/semantics/openAccessreponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãoinstacron:RCAAP2023-11-29T15:39:20Zoai:repositorio-aberto.up.pt:10216/70151Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireopendoar:71602024-03-20T00:28:53.214822Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informaçãofalse
dc.title.none.fl_str_mv Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems
title Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems
spellingShingle Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems
Miguel L. Silva
Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
title_short Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems
title_full Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems
title_fullStr Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems
title_full_unstemmed Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems
title_sort Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems
author Miguel L. Silva
author_facet Miguel L. Silva
João Canas Ferreira
author_role author
author2 João Canas Ferreira
author2_role author
dc.contributor.author.fl_str_mv Miguel L. Silva
João Canas Ferreira
dc.subject.por.fl_str_mv Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
topic Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
description This paper describes a tool that creates partially-reconfigurable modules from the bitstreams of individual component modules. The resulting modules are intended for use in applications that exploit partial dynamic reconfiguration. The tool is integrated in a design flow particularly aimed at dynamically-reconfigurable platform FPGAs. The corresponding design flow is described together with a basic run-time support system.
publishDate 2005
dc.date.none.fl_str_mv 2005
2005-01-01T00:00:00Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/book
format book
status_str publishedVersion
dc.identifier.uri.fl_str_mv https://hdl.handle.net/10216/70151
url https://hdl.handle.net/10216/70151
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv 10.1049/iet-cdt:20060056
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.source.none.fl_str_mv reponame:Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
instname:Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
instacron:RCAAP
instname_str Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
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collection Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
repository.name.fl_str_mv Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos) - Agência para a Sociedade do Conhecimento (UMIC) - FCT - Sociedade da Informação
repository.mail.fl_str_mv
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