Modeling and Analysis of Real Time Fixed Priority Scheduling using UML 2.0

Detalhes bibliográficos
Autor(a) principal: Hazra, Rumpa
Data de Publicação: 2013
Outros Autores: Dey, Shouvik, Kanjilal, Ananya, Bhattacharya, Swapan
Tipo de documento: Artigo
Idioma: eng
Título da fonte: INFOCOMP: Jornal de Ciência da Computação
Texto Completo: https://infocomp.dcc.ufla.br/index.php/infocomp/article/view/371
Resumo: Real Time Systems (RTS) interact with their environments using time constrained input/output signals. A functional misbehavior or a deviation from the specified time constraints may have catastrophic consequences. Hence, ensuring the correctness of such systems is extremely important and necessary. The increasing complexities of now-a-days ubiquitous real time systems require using an adequate modeling language. Unified Modeling Language (UML), a widely used visual object oriented modeling language, has proved to be effective and suitable for real time systems. The paper discusses the ability of UML and its profile to determine the schedulability of a fixed priority real time system. This paper puts stresses on the occurrence of deadlock in using the Priority Inheritance Protocol and prevention of such using the Priority Ceiling Protocol. Using UML 2.0 Sequence and Timing Diagrams, we model these two protocols and further, we analyze and compare these models.
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spelling Modeling and Analysis of Real Time Fixed Priority Scheduling using UML 2.0Real Time SystemsUMLPriority Ceiling ProtocolPriority Inheritance ProtocolDeadlockReal Time Systems (RTS) interact with their environments using time constrained input/output signals. A functional misbehavior or a deviation from the specified time constraints may have catastrophic consequences. Hence, ensuring the correctness of such systems is extremely important and necessary. The increasing complexities of now-a-days ubiquitous real time systems require using an adequate modeling language. Unified Modeling Language (UML), a widely used visual object oriented modeling language, has proved to be effective and suitable for real time systems. The paper discusses the ability of UML and its profile to determine the schedulability of a fixed priority real time system. This paper puts stresses on the occurrence of deadlock in using the Priority Inheritance Protocol and prevention of such using the Priority Ceiling Protocol. Using UML 2.0 Sequence and Timing Diagrams, we model these two protocols and further, we analyze and compare these models.Editora da UFLA2013-06-01info:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionapplication/pdfhttps://infocomp.dcc.ufla.br/index.php/infocomp/article/view/371INFOCOMP Journal of Computer Science; Vol. 12 No. 1 (2013): June, 2013; 36-481982-33631807-4545reponame:INFOCOMP: Jornal de Ciência da Computaçãoinstname:Universidade Federal de Lavras (UFLA)instacron:UFLAenghttps://infocomp.dcc.ufla.br/index.php/infocomp/article/view/371/355Copyright (c) 2016 INFOCOMP Journal of Computer Scienceinfo:eu-repo/semantics/openAccessHazra, RumpaDey, ShouvikKanjilal, AnanyaBhattacharya, Swapan2015-07-29T16:46:24Zoai:infocomp.dcc.ufla.br:article/371Revistahttps://infocomp.dcc.ufla.br/index.php/infocompPUBhttps://infocomp.dcc.ufla.br/index.php/infocomp/oaiinfocomp@dcc.ufla.br||apfreire@dcc.ufla.br1982-33631807-4545opendoar:2024-05-21T19:54:34.977091INFOCOMP: Jornal de Ciência da Computação - Universidade Federal de Lavras (UFLA)true
dc.title.none.fl_str_mv Modeling and Analysis of Real Time Fixed Priority Scheduling using UML 2.0
title Modeling and Analysis of Real Time Fixed Priority Scheduling using UML 2.0
spellingShingle Modeling and Analysis of Real Time Fixed Priority Scheduling using UML 2.0
Hazra, Rumpa
Real Time Systems
UML
Priority Ceiling Protocol
Priority Inheritance Protocol
Deadlock
title_short Modeling and Analysis of Real Time Fixed Priority Scheduling using UML 2.0
title_full Modeling and Analysis of Real Time Fixed Priority Scheduling using UML 2.0
title_fullStr Modeling and Analysis of Real Time Fixed Priority Scheduling using UML 2.0
title_full_unstemmed Modeling and Analysis of Real Time Fixed Priority Scheduling using UML 2.0
title_sort Modeling and Analysis of Real Time Fixed Priority Scheduling using UML 2.0
author Hazra, Rumpa
author_facet Hazra, Rumpa
Dey, Shouvik
Kanjilal, Ananya
Bhattacharya, Swapan
author_role author
author2 Dey, Shouvik
Kanjilal, Ananya
Bhattacharya, Swapan
author2_role author
author
author
dc.contributor.author.fl_str_mv Hazra, Rumpa
Dey, Shouvik
Kanjilal, Ananya
Bhattacharya, Swapan
dc.subject.por.fl_str_mv Real Time Systems
UML
Priority Ceiling Protocol
Priority Inheritance Protocol
Deadlock
topic Real Time Systems
UML
Priority Ceiling Protocol
Priority Inheritance Protocol
Deadlock
description Real Time Systems (RTS) interact with their environments using time constrained input/output signals. A functional misbehavior or a deviation from the specified time constraints may have catastrophic consequences. Hence, ensuring the correctness of such systems is extremely important and necessary. The increasing complexities of now-a-days ubiquitous real time systems require using an adequate modeling language. Unified Modeling Language (UML), a widely used visual object oriented modeling language, has proved to be effective and suitable for real time systems. The paper discusses the ability of UML and its profile to determine the schedulability of a fixed priority real time system. This paper puts stresses on the occurrence of deadlock in using the Priority Inheritance Protocol and prevention of such using the Priority Ceiling Protocol. Using UML 2.0 Sequence and Timing Diagrams, we model these two protocols and further, we analyze and compare these models.
publishDate 2013
dc.date.none.fl_str_mv 2013-06-01
dc.type.driver.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
format article
status_str publishedVersion
dc.identifier.uri.fl_str_mv https://infocomp.dcc.ufla.br/index.php/infocomp/article/view/371
url https://infocomp.dcc.ufla.br/index.php/infocomp/article/view/371
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv https://infocomp.dcc.ufla.br/index.php/infocomp/article/view/371/355
dc.rights.driver.fl_str_mv Copyright (c) 2016 INFOCOMP Journal of Computer Science
info:eu-repo/semantics/openAccess
rights_invalid_str_mv Copyright (c) 2016 INFOCOMP Journal of Computer Science
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv Editora da UFLA
publisher.none.fl_str_mv Editora da UFLA
dc.source.none.fl_str_mv INFOCOMP Journal of Computer Science; Vol. 12 No. 1 (2013): June, 2013; 36-48
1982-3363
1807-4545
reponame:INFOCOMP: Jornal de Ciência da Computação
instname:Universidade Federal de Lavras (UFLA)
instacron:UFLA
instname_str Universidade Federal de Lavras (UFLA)
instacron_str UFLA
institution UFLA
reponame_str INFOCOMP: Jornal de Ciência da Computação
collection INFOCOMP: Jornal de Ciência da Computação
repository.name.fl_str_mv INFOCOMP: Jornal de Ciência da Computação - Universidade Federal de Lavras (UFLA)
repository.mail.fl_str_mv infocomp@dcc.ufla.br||apfreire@dcc.ufla.br
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