Estudo e implementação de ip-cores para Criptografia simétrica baseada no Advanced encryption standard (AES)

• Autor(a) principal: Ramos Neto, Otacílio de Araújo
• Data de Publicação: 2013
• Tipo de documento: Dissertação
• Idioma: por
• Título da fonte: Biblioteca Digital de Teses e Dissertações da UFPB
• Texto Completo: https://repositorio.ufpb.br/jspui/handle/tede/6092
• topic: Advanced Encryption Standard - AES; Criptografia simétrica; Circuito integrado; S-Box; Symmetric encryption; Integrated circuit; CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO

This work addresses data encryption using Rijndael symmetric key encryption algorithm , which is used in Advanced Encryption Standard - AES. AES has massively widespread in computing, communications, and broadcast media applications, due to its robustness. By intensively using of all flavors and sizes of devices and networks, the AES has become the standard at the time of implementation and deployment of these applications when the major requirement, in addition to performance, is security, i.e. virtually all of those applications nowadays. In systems equipped with modern processors, even those on small devices, it is common to find some that perform the encryption and decryption procedures in software. With the "explosive" spread of addition of security layers in almost everything that is processed inside and outside of the devices, even on systems equipped with powerful computing resources, the possibility of performing these layers on (small) additional hardware resources, developed with specific purpose, has become attractive. This dissertation presents a study of the theoretical foundations involving AES, some architectures and implementations based on it and documented in the recent technical and scientific literature, as well as the methodologies and requirements for the development of its hardware implementation, in particular, focusing on mobile systems, where performance has to be achieved in low power consumption and small area scenarios. Reference models have been developed and functionally validated in high-level languages for each hierarchical architectural level compiled from the mentioned study. As a proof of concept, this work consisted in undertaking a project of an intellectual property of digital integrated circuit core (IP core) for the encryption/decryption procedures of AES, starting from the pseudocode level of the algorithms and going to the level of a digital integrated circuit core. Among the solutions studied from recent literature, modules and operations that could be replicated and/or reused were identified. A microarchitecture for the full AES was implemented hierarchically to the core level with standard cells placed and routed. The work also offers three implementation options for the block identified as the most complex: the S-Box. Results of performance and area were then presented and compared with those of literature.