New techniques for improving the performance of the lockstep architecture for SEEs mitigation in FPGA embedded processors
Autor(a) principal: | |
---|---|
Data de Publicação: | 2009 |
Outros Autores: | , , , |
Tipo de documento: | Artigo |
Idioma: | eng |
Título da fonte: | Repositório Institucional da UFRGS |
Texto Completo: | http://hdl.handle.net/10183/27627 |
Resumo: | The growing availability of embedded processors inside FPGAs provides unprecedented flexibility for system designers. The use of such devices for space or mission critical applications, however, is being delayed by the lack of effective low cost techniques to mitigate radiation induced errors. In this paper a non invasive approach for the implementation of fault tolerant systems based on COTS processors embedded in FPGAs, using lockstep in conjunction with checkpoint and rollback recovery, is presented. The proposed approach does not require modifications in the processor architecture or in the application software. The experimental validation of this approach through fault injection is described, the corresponding results are discussed, and the addition of a write history table as a means to reduce the performance overhead imposed by previous implementations is proposed and evaluated. |
id |
UFRGS-2_2b137738a8d7120923d17e0fc9189e26 |
---|---|
oai_identifier_str |
oai:www.lume.ufrgs.br:10183/27627 |
network_acronym_str |
UFRGS-2 |
network_name_str |
Repositório Institucional da UFRGS |
repository_id_str |
|
spelling |
Abate, F.Sterpone, LucaLisboa, Carlos Arthur LangCarro, LuigiViolante, Massimo2011-01-29T06:00:45Z20090018-9499http://hdl.handle.net/10183/27627000719345The growing availability of embedded processors inside FPGAs provides unprecedented flexibility for system designers. The use of such devices for space or mission critical applications, however, is being delayed by the lack of effective low cost techniques to mitigate radiation induced errors. In this paper a non invasive approach for the implementation of fault tolerant systems based on COTS processors embedded in FPGAs, using lockstep in conjunction with checkpoint and rollback recovery, is presented. The proposed approach does not require modifications in the processor architecture or in the application software. The experimental validation of this approach through fault injection is described, the corresponding results are discussed, and the addition of a write history table as a means to reduce the performance overhead imposed by previous implementations is proposed and evaluated.application/pdfengIEEE transactions on nuclear science. New York. Vol. 56, no 4 (Aug. 2009), p. 1992-2000MicroeletrônicaSistemas embarcadosEmbedded processors reliabilitySingle event effectsLockstepCheckpointRollback recoveryFault injectionNew techniques for improving the performance of the lockstep architecture for SEEs mitigation in FPGA embedded processorsEstrangeiroinfo:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/openAccessreponame:Repositório Institucional da UFRGSinstname:Universidade Federal do Rio Grande do Sul (UFRGS)instacron:UFRGSTEXT000719345.pdf.txt000719345.pdf.txtExtracted Texttext/plain51363http://www.lume.ufrgs.br/bitstream/10183/27627/2/000719345.pdf.txt0660a97a1f128936f780d28c0103cf4dMD52ORIGINAL000719345.pdf000719345.pdfTexto completo (inglês)application/pdf171846http://www.lume.ufrgs.br/bitstream/10183/27627/1/000719345.pdf4cf1bfbfaa3416de69555c06bddecd0cMD51THUMBNAIL000719345.pdf.jpg000719345.pdf.jpgGenerated Thumbnailimage/jpeg2343http://www.lume.ufrgs.br/bitstream/10183/27627/3/000719345.pdf.jpg34a1bc2958f4c80a92397356a47b1101MD5310183/276272021-05-26 04:35:06.051289oai:www.lume.ufrgs.br:10183/27627Repositório de PublicaçõesPUBhttps://lume.ufrgs.br/oai/requestopendoar:2021-05-26T07:35:06Repositório Institucional da UFRGS - Universidade Federal do Rio Grande do Sul (UFRGS)false |
dc.title.pt_BR.fl_str_mv |
New techniques for improving the performance of the lockstep architecture for SEEs mitigation in FPGA embedded processors |
title |
New techniques for improving the performance of the lockstep architecture for SEEs mitigation in FPGA embedded processors |
spellingShingle |
New techniques for improving the performance of the lockstep architecture for SEEs mitigation in FPGA embedded processors Abate, F. Microeletrônica Sistemas embarcados Embedded processors reliability Single event effects Lockstep Checkpoint Rollback recovery Fault injection |
title_short |
New techniques for improving the performance of the lockstep architecture for SEEs mitigation in FPGA embedded processors |
title_full |
New techniques for improving the performance of the lockstep architecture for SEEs mitigation in FPGA embedded processors |
title_fullStr |
New techniques for improving the performance of the lockstep architecture for SEEs mitigation in FPGA embedded processors |
title_full_unstemmed |
New techniques for improving the performance of the lockstep architecture for SEEs mitigation in FPGA embedded processors |
title_sort |
New techniques for improving the performance of the lockstep architecture for SEEs mitigation in FPGA embedded processors |
author |
Abate, F. |
author_facet |
Abate, F. Sterpone, Luca Lisboa, Carlos Arthur Lang Carro, Luigi Violante, Massimo |
author_role |
author |
author2 |
Sterpone, Luca Lisboa, Carlos Arthur Lang Carro, Luigi Violante, Massimo |
author2_role |
author author author author |
dc.contributor.author.fl_str_mv |
Abate, F. Sterpone, Luca Lisboa, Carlos Arthur Lang Carro, Luigi Violante, Massimo |
dc.subject.por.fl_str_mv |
Microeletrônica Sistemas embarcados |
topic |
Microeletrônica Sistemas embarcados Embedded processors reliability Single event effects Lockstep Checkpoint Rollback recovery Fault injection |
dc.subject.eng.fl_str_mv |
Embedded processors reliability Single event effects Lockstep Checkpoint Rollback recovery Fault injection |
description |
The growing availability of embedded processors inside FPGAs provides unprecedented flexibility for system designers. The use of such devices for space or mission critical applications, however, is being delayed by the lack of effective low cost techniques to mitigate radiation induced errors. In this paper a non invasive approach for the implementation of fault tolerant systems based on COTS processors embedded in FPGAs, using lockstep in conjunction with checkpoint and rollback recovery, is presented. The proposed approach does not require modifications in the processor architecture or in the application software. The experimental validation of this approach through fault injection is described, the corresponding results are discussed, and the addition of a write history table as a means to reduce the performance overhead imposed by previous implementations is proposed and evaluated. |
publishDate |
2009 |
dc.date.issued.fl_str_mv |
2009 |
dc.date.accessioned.fl_str_mv |
2011-01-29T06:00:45Z |
dc.type.driver.fl_str_mv |
Estrangeiro info:eu-repo/semantics/article |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
format |
article |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://hdl.handle.net/10183/27627 |
dc.identifier.issn.pt_BR.fl_str_mv |
0018-9499 |
dc.identifier.nrb.pt_BR.fl_str_mv |
000719345 |
identifier_str_mv |
0018-9499 000719345 |
url |
http://hdl.handle.net/10183/27627 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.ispartof.pt_BR.fl_str_mv |
IEEE transactions on nuclear science. New York. Vol. 56, no 4 (Aug. 2009), p. 1992-2000 |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.format.none.fl_str_mv |
application/pdf |
dc.source.none.fl_str_mv |
reponame:Repositório Institucional da UFRGS instname:Universidade Federal do Rio Grande do Sul (UFRGS) instacron:UFRGS |
instname_str |
Universidade Federal do Rio Grande do Sul (UFRGS) |
instacron_str |
UFRGS |
institution |
UFRGS |
reponame_str |
Repositório Institucional da UFRGS |
collection |
Repositório Institucional da UFRGS |
bitstream.url.fl_str_mv |
http://www.lume.ufrgs.br/bitstream/10183/27627/2/000719345.pdf.txt http://www.lume.ufrgs.br/bitstream/10183/27627/1/000719345.pdf http://www.lume.ufrgs.br/bitstream/10183/27627/3/000719345.pdf.jpg |
bitstream.checksum.fl_str_mv |
0660a97a1f128936f780d28c0103cf4d 4cf1bfbfaa3416de69555c06bddecd0c 34a1bc2958f4c80a92397356a47b1101 |
bitstream.checksumAlgorithm.fl_str_mv |
MD5 MD5 MD5 |
repository.name.fl_str_mv |
Repositório Institucional da UFRGS - Universidade Federal do Rio Grande do Sul (UFRGS) |
repository.mail.fl_str_mv |
|
_version_ |
1801224725081358336 |