MOSFET ZTC condition analysis for a self-biased current reference design
Autor(a) principal: | |
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Data de Publicação: | 2015 |
Outros Autores: | , , , |
Tipo de documento: | Artigo |
Idioma: | eng |
Título da fonte: | Repositório Institucional da UFRGS |
Texto Completo: | http://hdl.handle.net/10183/259654 |
Resumo: | In this paper a self-biased current reference based on Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) Zero Temperature Coefficient (ZTC) condition is proposed. It can be imple mented in any Complementary Metal-Oxide-Semiconductor (CMOS) fabrication process and pro vides another alternative to design current references. In order to support the circuit design, ZTC condition is analyzed using a MOSFET model that is continuous from weak to strong inversion, show ing that this condition always occurs from moderate to strong inversion in any CMOS process. The proposed topology was designed in a 180 nm process, operates with a supply voltage from 1.4V to 1.8 V and occupies around 0.010mm2 of silicon area. From circuit simulations our reference showed a temperature coefficient (TC) of 15 ppm/o C from -40 to +85o C, and a fabrication process sensitivity of σ/μ = 4.5% for the current reference, including average process and local mismatch variability analysis. The simulated power supply sensitivity is estimated around 1%/V. |
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Toledo, Pedro Filipe Leite Correia deKlimach, Hamilton DuarteCordova Vivas, David JavierBampi, SergioFabris, Eric Ericson2023-06-30T03:31:19Z20151807-1953http://hdl.handle.net/10183/259654000983871In this paper a self-biased current reference based on Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) Zero Temperature Coefficient (ZTC) condition is proposed. It can be imple mented in any Complementary Metal-Oxide-Semiconductor (CMOS) fabrication process and pro vides another alternative to design current references. In order to support the circuit design, ZTC condition is analyzed using a MOSFET model that is continuous from weak to strong inversion, show ing that this condition always occurs from moderate to strong inversion in any CMOS process. The proposed topology was designed in a 180 nm process, operates with a supply voltage from 1.4V to 1.8 V and occupies around 0.010mm2 of silicon area. From circuit simulations our reference showed a temperature coefficient (TC) of 15 ppm/o C from -40 to +85o C, and a fabrication process sensitivity of σ/μ = 4.5% for the current reference, including average process and local mismatch variability analysis. The simulated power supply sensitivity is estimated around 1%/V.application/pdfengJournal of integrated circuits and systems. Porto Alegre, RS. Vol. 10, n. 2 (Aug. 2015), p. 103-112MosfetSemicondutoresSimulação numéricaMétodo de Monte CarloMOSFET ZTC conditionCurrent reference sourceLow temperature coefficientMOSFET ZTC condition analysis for a self-biased current reference designinfo:eu-repo/semantics/articleinfo:eu-repo/semantics/otherinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/openAccessreponame:Repositório Institucional da UFRGSinstname:Universidade Federal do Rio Grande do Sul (UFRGS)instacron:UFRGSTEXT000983871.pdf.txt000983871.pdf.txtExtracted Texttext/plain27910http://www.lume.ufrgs.br/bitstream/10183/259654/2/000983871.pdf.txt23c562bf0d45cde007d25b7aec000447MD52ORIGINAL000983871.pdfTexto completo (inglês)application/pdf2531505http://www.lume.ufrgs.br/bitstream/10183/259654/1/000983871.pdf9f1e7941eb313568297047fbcbc0f245MD5110183/2596542023-07-01 03:37:55.086161oai:www.lume.ufrgs.br:10183/259654Repositório de PublicaçõesPUBhttps://lume.ufrgs.br/oai/requestopendoar:2023-07-01T06:37:55Repositório Institucional da UFRGS - Universidade Federal do Rio Grande do Sul (UFRGS)false |
dc.title.pt_BR.fl_str_mv |
MOSFET ZTC condition analysis for a self-biased current reference design |
title |
MOSFET ZTC condition analysis for a self-biased current reference design |
spellingShingle |
MOSFET ZTC condition analysis for a self-biased current reference design Toledo, Pedro Filipe Leite Correia de Mosfet Semicondutores Simulação numérica Método de Monte Carlo MOSFET ZTC condition Current reference source Low temperature coefficient |
title_short |
MOSFET ZTC condition analysis for a self-biased current reference design |
title_full |
MOSFET ZTC condition analysis for a self-biased current reference design |
title_fullStr |
MOSFET ZTC condition analysis for a self-biased current reference design |
title_full_unstemmed |
MOSFET ZTC condition analysis for a self-biased current reference design |
title_sort |
MOSFET ZTC condition analysis for a self-biased current reference design |
author |
Toledo, Pedro Filipe Leite Correia de |
author_facet |
Toledo, Pedro Filipe Leite Correia de Klimach, Hamilton Duarte Cordova Vivas, David Javier Bampi, Sergio Fabris, Eric Ericson |
author_role |
author |
author2 |
Klimach, Hamilton Duarte Cordova Vivas, David Javier Bampi, Sergio Fabris, Eric Ericson |
author2_role |
author author author author |
dc.contributor.author.fl_str_mv |
Toledo, Pedro Filipe Leite Correia de Klimach, Hamilton Duarte Cordova Vivas, David Javier Bampi, Sergio Fabris, Eric Ericson |
dc.subject.por.fl_str_mv |
Mosfet Semicondutores Simulação numérica Método de Monte Carlo |
topic |
Mosfet Semicondutores Simulação numérica Método de Monte Carlo MOSFET ZTC condition Current reference source Low temperature coefficient |
dc.subject.eng.fl_str_mv |
MOSFET ZTC condition Current reference source Low temperature coefficient |
description |
In this paper a self-biased current reference based on Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) Zero Temperature Coefficient (ZTC) condition is proposed. It can be imple mented in any Complementary Metal-Oxide-Semiconductor (CMOS) fabrication process and pro vides another alternative to design current references. In order to support the circuit design, ZTC condition is analyzed using a MOSFET model that is continuous from weak to strong inversion, show ing that this condition always occurs from moderate to strong inversion in any CMOS process. The proposed topology was designed in a 180 nm process, operates with a supply voltage from 1.4V to 1.8 V and occupies around 0.010mm2 of silicon area. From circuit simulations our reference showed a temperature coefficient (TC) of 15 ppm/o C from -40 to +85o C, and a fabrication process sensitivity of σ/μ = 4.5% for the current reference, including average process and local mismatch variability analysis. The simulated power supply sensitivity is estimated around 1%/V. |
publishDate |
2015 |
dc.date.issued.fl_str_mv |
2015 |
dc.date.accessioned.fl_str_mv |
2023-06-30T03:31:19Z |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/article info:eu-repo/semantics/other |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
format |
article |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://hdl.handle.net/10183/259654 |
dc.identifier.issn.pt_BR.fl_str_mv |
1807-1953 |
dc.identifier.nrb.pt_BR.fl_str_mv |
000983871 |
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http://hdl.handle.net/10183/259654 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.ispartof.pt_BR.fl_str_mv |
Journal of integrated circuits and systems. Porto Alegre, RS. Vol. 10, n. 2 (Aug. 2015), p. 103-112 |
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info:eu-repo/semantics/openAccess |
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openAccess |
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