Tolerância a Falhas na Rede em Chip SPINoSys

• Autor(a) principal: Ribeiro, Jandson de Oliveira Cavalcanti
• Data de Publicação: 2017
• Tipo de documento: Trabalho de conclusão de curso
• Idioma: por
• Título da fonte: Repositório Institucional da UFRN
• Texto Completo: https://repositorio.ufrn.br/handle/123456789/34185
• topic: rede em chip; tentativa; IPNoSys; SPINoSys; Tolerância a falhas; SoC; System on Chip; MPSoC; NoC; Network on Chip; switch; bypass; Fault Tolerance

With the advances in the manufacture of integrated circuits, chips with multiple processing cores appeared. With the increase in the number of cores within a single chip, the use of buses as solution for communication was no longer valid. In order to enable the communication between the cores, it began to use peer to peer communication channels, this communication model is called Network on Chip. The use of network on chip enabled to create different types of networks that differ in their communication protocols. However, the use of these channels made it possible, in addition to the possibility of failures during processing, that there were also failures at the time of data transmission in the network. Thus, with the emergence of new networks, there is a need to develop methods that keep the chip working, even in case of failure of some component. This work proposes a fault tolerance method for SPINoSys, an Netowrk on Chip created from IPNoSys, which introduced the idea of joining processing units with routing units, making a single unit responsible for executing and transmitting instructions. This method, in short, seeks to perform data transmission through retries, where each uses different routes, while also maintaining control in the network and the ability to know when, even with all attempts, a message can not be transmitted.