Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks
Autor(a) principal: | |
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Data de Publicação: | 2011 |
Outros Autores: | , , , |
Tipo de documento: | Artigo |
Idioma: | eng |
Título da fonte: | LOCUS Repositório Institucional da UFV |
Texto Completo: | https://doi.org/10.1016/j.sysarc.2011.03.006 http://www.locus.ufv.br/handle/123456789/22089 |
Resumo: | Reconfigurable computing architectures are commonly used for accelerating applications and/or for achieving energy savings. However, most reconfigurable computing architectures suffer from computationally demanding placement and routing (P&R) steps. This problem may disable their use in systems requiring dynamic compilation (e.g., to guarantee application portability in embedded systems). Bearing in mind the simplification of P&R steps, this paper presents and analyzes a coarse-grained reconfigurable array (CGRA) extended with global multistage interconnect networks, specifically Omega Networks. We show that integrating one or two Omega Networks in a CGRA permits to simplify the P&R stage resulting in both low hardware resource overhead and low performance degradation (18% for an 8 × 8 array). We compare the proposed CGRA, which integrates one or two Omega Networks, with a CGRA based on a grid of processing elements with reach neighbor interconnections and with a torus topology. The execution time needed to perform the P&R stage for the two array architectures shows that the array using two Omega Networks needs a far simpler and faster P&R. The P&R stage in our approach completed on average in about 16× less time for the 17 benchmarks used. Similar fast approaches needed CGRAs with more complex interconnect resources in order to allow most of the benchmarks used to be successfully placed and routed. |
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Ferreira, Ricardo S.Cardoso, João M. P.Damiany, AlexVendramini, JulioTeixeira, Tiago2018-10-01T11:57:11Z2018-10-01T11:57:11Z2011-0913837621https://doi.org/10.1016/j.sysarc.2011.03.006http://www.locus.ufv.br/handle/123456789/22089Reconfigurable computing architectures are commonly used for accelerating applications and/or for achieving energy savings. However, most reconfigurable computing architectures suffer from computationally demanding placement and routing (P&R) steps. This problem may disable their use in systems requiring dynamic compilation (e.g., to guarantee application portability in embedded systems). Bearing in mind the simplification of P&R steps, this paper presents and analyzes a coarse-grained reconfigurable array (CGRA) extended with global multistage interconnect networks, specifically Omega Networks. We show that integrating one or two Omega Networks in a CGRA permits to simplify the P&R stage resulting in both low hardware resource overhead and low performance degradation (18% for an 8 × 8 array). We compare the proposed CGRA, which integrates one or two Omega Networks, with a CGRA based on a grid of processing elements with reach neighbor interconnections and with a torus topology. The execution time needed to perform the P&R stage for the two array architectures shows that the array using two Omega Networks needs a far simpler and faster P&R. The P&R stage in our approach completed on average in about 16× less time for the 17 benchmarks used. Similar fast approaches needed CGRAs with more complex interconnect resources in order to allow most of the benchmarks used to be successfully placed and routed.engJournal of Systems Architecturev. 57, n. 8, p. 761- 777, set. 2011Elsevier B.V.info:eu-repo/semantics/openAccessCoarse-grained reconfigurable arraysMultistage interconnection networksPlacement and routingFPGAsFast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networksinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfreponame:LOCUS Repositório Institucional da UFVinstname:Universidade Federal de Viçosa (UFV)instacron:UFVORIGINALartigo.pdfartigo.pdftexto completoapplication/pdf1808272https://locus.ufv.br//bitstream/123456789/22089/1/artigo.pdfc8d25354b6cdaee3e880f0c69fb4a565MD51LICENSElicense.txtlicense.txttext/plain; charset=utf-81748https://locus.ufv.br//bitstream/123456789/22089/2/license.txt8a4605be74aa9ea9d79846c1fba20a33MD52THUMBNAILartigo.pdf.jpgartigo.pdf.jpgIM Thumbnailimage/jpeg5432https://locus.ufv.br//bitstream/123456789/22089/3/artigo.pdf.jpg890730e154125e1ea2d6df544ae41a28MD53123456789/220892018-10-01 23:00:40.568oai:locus.ufv.br:123456789/22089Tk9URTogUExBQ0UgWU9VUiBPV04gTElDRU5TRSBIRVJFClRoaXMgc2FtcGxlIGxpY2Vuc2UgaXMgcHJvdmlkZWQgZm9yIGluZm9ybWF0aW9uYWwgcHVycG9zZXMgb25seS4KCk5PTi1FWENMVVNJVkUgRElTVFJJQlVUSU9OIExJQ0VOU0UKCkJ5IHNpZ25pbmcgYW5kIHN1Ym1pdHRpbmcgdGhpcyBsaWNlbnNlLCB5b3UgKHRoZSBhdXRob3Iocykgb3IgY29weXJpZ2h0Cm93bmVyKSBncmFudHMgdG8gRFNwYWNlIFVuaXZlcnNpdHkgKERTVSkgdGhlIG5vbi1leGNsdXNpdmUgcmlnaHQgdG8gcmVwcm9kdWNlLAp0cmFuc2xhdGUgKGFzIGRlZmluZWQgYmVsb3cpLCBhbmQvb3IgZGlzdHJpYnV0ZSB5b3VyIHN1Ym1pc3Npb24gKGluY2x1ZGluZwp0aGUgYWJzdHJhY3QpIHdvcmxkd2lkZSBpbiBwcmludCBhbmQgZWxlY3Ryb25pYyBmb3JtYXQgYW5kIGluIGFueSBtZWRpdW0sCmluY2x1ZGluZyBidXQgbm90IGxpbWl0ZWQgdG8gYXVkaW8gb3IgdmlkZW8uCgpZb3UgYWdyZWUgdGhhdCBEU1UgbWF5LCB3aXRob3V0IGNoYW5naW5nIHRoZSBjb250ZW50LCB0cmFuc2xhdGUgdGhlCnN1Ym1pc3Npb24gdG8gYW55IG1lZGl1bSBvciBmb3JtYXQgZm9yIHRoZSBwdXJwb3NlIG9mIHByZXNlcnZhdGlvbi4KCllvdSBhbHNvIGFncmVlIHRoYXQgRFNVIG1heSBrZWVwIG1vcmUgdGhhbiBvbmUgY29weSBvZiB0aGlzIHN1Ym1pc3Npb24gZm9yCnB1cnBvc2VzIG9mIHNlY3VyaXR5LCBiYWNrLXVwIGFuZCBwcmVzZXJ2YXRpb24uCgpZb3UgcmVwcmVzZW50IHRoYXQgdGhlIHN1Ym1pc3Npb24gaXMgeW91ciBvcmlnaW5hbCB3b3JrLCBhbmQgdGhhdCB5b3UgaGF2ZQp0aGUgcmlnaHQgdG8gZ3JhbnQgdGhlIHJpZ2h0cyBjb250YWluZWQgaW4gdGhpcyBsaWNlbnNlLiBZb3UgYWxzbyByZXByZXNlbnQKdGhhdCB5b3VyIHN1Ym1pc3Npb24gZG9lcyBub3QsIHRvIHRoZSBiZXN0IG9mIHlvdXIga25vd2xlZGdlLCBpbmZyaW5nZSB1cG9uCmFueW9uZSdzIGNvcHlyaWdodC4KCklmIHRoZSBzdWJtaXNzaW9uIGNvbnRhaW5zIG1hdGVyaWFsIGZvciB3aGljaCB5b3UgZG8gbm90IGhvbGQgY29weXJpZ2h0LAp5b3UgcmVwcmVzZW50IHRoYXQgeW91IGhhdmUgb2J0YWluZWQgdGhlIHVucmVzdHJpY3RlZCBwZXJtaXNzaW9uIG9mIHRoZQpjb3B5cmlnaHQgb3duZXIgdG8gZ3JhbnQgRFNVIHRoZSByaWdodHMgcmVxdWlyZWQgYnkgdGhpcyBsaWNlbnNlLCBhbmQgdGhhdApzdWNoIHRoaXJkLXBhcnR5IG93bmVkIG1hdGVyaWFsIGlzIGNsZWFybHkgaWRlbnRpZmllZCBhbmQgYWNrbm93bGVkZ2VkCndpdGhpbiB0aGUgdGV4dCBvciBjb250ZW50IG9mIHRoZSBzdWJtaXNzaW9uLgoKSUYgVEhFIFNVQk1JU1NJT04gSVMgQkFTRUQgVVBPTiBXT1JLIFRIQVQgSEFTIEJFRU4gU1BPTlNPUkVEIE9SIFNVUFBPUlRFRApCWSBBTiBBR0VOQ1kgT1IgT1JHQU5JWkFUSU9OIE9USEVSIFRIQU4gRFNVLCBZT1UgUkVQUkVTRU5UIFRIQVQgWU9VIEhBVkUKRlVMRklMTEVEIEFOWSBSSUdIVCBPRiBSRVZJRVcgT1IgT1RIRVIgT0JMSUdBVElPTlMgUkVRVUlSRUQgQlkgU1VDSApDT05UUkFDVCBPUiBBR1JFRU1FTlQuCgpEU1Ugd2lsbCBjbGVhcmx5IGlkZW50aWZ5IHlvdXIgbmFtZShzKSBhcyB0aGUgYXV0aG9yKHMpIG9yIG93bmVyKHMpIG9mIHRoZQpzdWJtaXNzaW9uLCBhbmQgd2lsbCBub3QgbWFrZSBhbnkgYWx0ZXJhdGlvbiwgb3RoZXIgdGhhbiBhcyBhbGxvd2VkIGJ5IHRoaXMKbGljZW5zZSwgdG8geW91ciBzdWJtaXNzaW9uLgo=Repositório InstitucionalPUBhttps://www.locus.ufv.br/oai/requestfabiojreis@ufv.bropendoar:21452018-10-02T02:00:40LOCUS Repositório Institucional da UFV - Universidade Federal de Viçosa (UFV)false |
dc.title.en.fl_str_mv |
Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks |
title |
Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks |
spellingShingle |
Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks Ferreira, Ricardo S. Coarse-grained reconfigurable arrays Multistage interconnection networks Placement and routing FPGAs |
title_short |
Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks |
title_full |
Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks |
title_fullStr |
Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks |
title_full_unstemmed |
Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks |
title_sort |
Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks |
author |
Ferreira, Ricardo S. |
author_facet |
Ferreira, Ricardo S. Cardoso, João M. P. Damiany, Alex Vendramini, Julio Teixeira, Tiago |
author_role |
author |
author2 |
Cardoso, João M. P. Damiany, Alex Vendramini, Julio Teixeira, Tiago |
author2_role |
author author author author |
dc.contributor.author.fl_str_mv |
Ferreira, Ricardo S. Cardoso, João M. P. Damiany, Alex Vendramini, Julio Teixeira, Tiago |
dc.subject.pt-BR.fl_str_mv |
Coarse-grained reconfigurable arrays Multistage interconnection networks Placement and routing FPGAs |
topic |
Coarse-grained reconfigurable arrays Multistage interconnection networks Placement and routing FPGAs |
description |
Reconfigurable computing architectures are commonly used for accelerating applications and/or for achieving energy savings. However, most reconfigurable computing architectures suffer from computationally demanding placement and routing (P&R) steps. This problem may disable their use in systems requiring dynamic compilation (e.g., to guarantee application portability in embedded systems). Bearing in mind the simplification of P&R steps, this paper presents and analyzes a coarse-grained reconfigurable array (CGRA) extended with global multistage interconnect networks, specifically Omega Networks. We show that integrating one or two Omega Networks in a CGRA permits to simplify the P&R stage resulting in both low hardware resource overhead and low performance degradation (18% for an 8 × 8 array). We compare the proposed CGRA, which integrates one or two Omega Networks, with a CGRA based on a grid of processing elements with reach neighbor interconnections and with a torus topology. The execution time needed to perform the P&R stage for the two array architectures shows that the array using two Omega Networks needs a far simpler and faster P&R. The P&R stage in our approach completed on average in about 16× less time for the 17 benchmarks used. Similar fast approaches needed CGRAs with more complex interconnect resources in order to allow most of the benchmarks used to be successfully placed and routed. |
publishDate |
2011 |
dc.date.issued.fl_str_mv |
2011-09 |
dc.date.accessioned.fl_str_mv |
2018-10-01T11:57:11Z |
dc.date.available.fl_str_mv |
2018-10-01T11:57:11Z |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/article |
format |
article |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
https://doi.org/10.1016/j.sysarc.2011.03.006 http://www.locus.ufv.br/handle/123456789/22089 |
dc.identifier.issn.none.fl_str_mv |
13837621 |
identifier_str_mv |
13837621 |
url |
https://doi.org/10.1016/j.sysarc.2011.03.006 http://www.locus.ufv.br/handle/123456789/22089 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.ispartofseries.pt-BR.fl_str_mv |
v. 57, n. 8, p. 761- 777, set. 2011 |
dc.rights.driver.fl_str_mv |
Elsevier B.V. info:eu-repo/semantics/openAccess |
rights_invalid_str_mv |
Elsevier B.V. |
eu_rights_str_mv |
openAccess |
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application/pdf |
dc.publisher.none.fl_str_mv |
Journal of Systems Architecture |
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Journal of Systems Architecture |
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LOCUS Repositório Institucional da UFV |
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