Simplified Small-Signal Model for Output Voltage Control of Asymmetric Cascaded H-Bridge Multilevel Inverter

Detalhes bibliográficos
Autor(a) principal: Curi Busarello, Tiago Davi
Data de Publicação: 2018
Outros Autores: Mortezaei, Ali, Morales Paredes, Helmo Kelis [UNESP], Al-Durra, Ahmed, Pomilio, Jose Antenor, Simoes, Marcelo Godoy
Tipo de documento: Artigo
Idioma: eng
Título da fonte: Repositório Institucional da UNESP
Texto Completo: http://dx.doi.org/10.1109/TPEL.2017.2704919
http://hdl.handle.net/11449/165968
Resumo: This paper proposes a simplified small-signal model for output voltage control of a single-phase asymmetrical cascaded H-bridge multilevel inverter (ACHMI). The ACHMI is an n-series connected H-bridge converter, each one with a unique value at the dc link and usually scaled at {1:2:6:...} or {1:3:9:...}. By assuming that the small-signal variation component is equal in all n converter terminal ports, a simplified small-signal model is obtained. This assumption is carefully described and justified. To verify the veracity of the proposed model, two distinct control strategies are applied. One is a single-loop control scheme based on a modified proportional-integral (PI) controller. The other one is a double-loop control scheme based on a PI controller with feedforward action of the load current. Both controllers are tuned based on the dynamic behavior of the proposed model. Since the designed controllers based on the simplified model make the ACHMI output voltage to follow the reference without steady-state error, the proposed simplified model truly represents the inverter. Experimental results show the efficacy of the simplified model of the ACHMI through the two mentioned control strategies as well as the ACHMI installed in a microgrid.
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spelling Simplified Small-Signal Model for Output Voltage Control of Asymmetric Cascaded H-Bridge Multilevel InverterModelingmultilevel invertersmall-signalstair-case modulationvoltage controlThis paper proposes a simplified small-signal model for output voltage control of a single-phase asymmetrical cascaded H-bridge multilevel inverter (ACHMI). The ACHMI is an n-series connected H-bridge converter, each one with a unique value at the dc link and usually scaled at {1:2:6:...} or {1:3:9:...}. By assuming that the small-signal variation component is equal in all n converter terminal ports, a simplified small-signal model is obtained. This assumption is carefully described and justified. To verify the veracity of the proposed model, two distinct control strategies are applied. One is a single-loop control scheme based on a modified proportional-integral (PI) controller. The other one is a double-loop control scheme based on a PI controller with feedforward action of the load current. Both controllers are tuned based on the dynamic behavior of the proposed model. Since the designed controllers based on the simplified model make the ACHMI output voltage to follow the reference without steady-state error, the proposed simplified model truly represents the inverter. Experimental results show the efficacy of the simplified model of the ACHMI through the two mentioned control strategies as well as the ACHMI installed in a microgrid.Univ Fed Santa Catarina, Dept Engn, BR-89065300 Blumenau, BrazilColorado Sch Mines, Dept Elect Engn & Comp Sci, Golden, CO 80401 USAUniv Estadual Paulista, BR-18087180 Sorocaba, BrazilKhalifa Univ Sci & Technol, Dept Elect & Comp Engn, Abu Dhabi 127788, U Arab EmiratesUniv Estadual Campinas, Sch Elect & Comp Engn, BR-13083852 Campinas, SP, BrazilUniv Estadual Paulista, BR-18087180 Sorocaba, BrazilIeee-inst Electrical Electronics Engineers IncUniversidade Federal de Santa Catarina (UFSC)Colorado Sch MinesUniversidade Estadual Paulista (Unesp)Khalifa Univ Sci & TechnolUniversidade Estadual de Campinas (UNICAMP)Curi Busarello, Tiago DaviMortezaei, AliMorales Paredes, Helmo Kelis [UNESP]Al-Durra, AhmedPomilio, Jose AntenorSimoes, Marcelo Godoy2018-11-29T05:57:15Z2018-11-29T05:57:15Z2018-04-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/article3509-3519application/pdfhttp://dx.doi.org/10.1109/TPEL.2017.2704919Ieee Transactions On Power Electronics. Piscataway: Ieee-inst Electrical Electronics Engineers Inc, v. 33, n. 4, p. 3509-3519, 2018.0885-8993http://hdl.handle.net/11449/16596810.1109/TPEL.2017.2704919WOS:000422933400065WOS000422933400065.pdfWeb of Sciencereponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPengIeee Transactions On Power Electronicsinfo:eu-repo/semantics/openAccess2023-11-01T06:11:48Zoai:repositorio.unesp.br:11449/165968Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462023-11-01T06:11:48Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false
dc.title.none.fl_str_mv Simplified Small-Signal Model for Output Voltage Control of Asymmetric Cascaded H-Bridge Multilevel Inverter
title Simplified Small-Signal Model for Output Voltage Control of Asymmetric Cascaded H-Bridge Multilevel Inverter
spellingShingle Simplified Small-Signal Model for Output Voltage Control of Asymmetric Cascaded H-Bridge Multilevel Inverter
Curi Busarello, Tiago Davi
Modeling
multilevel inverter
small-signal
stair-case modulation
voltage control
title_short Simplified Small-Signal Model for Output Voltage Control of Asymmetric Cascaded H-Bridge Multilevel Inverter
title_full Simplified Small-Signal Model for Output Voltage Control of Asymmetric Cascaded H-Bridge Multilevel Inverter
title_fullStr Simplified Small-Signal Model for Output Voltage Control of Asymmetric Cascaded H-Bridge Multilevel Inverter
title_full_unstemmed Simplified Small-Signal Model for Output Voltage Control of Asymmetric Cascaded H-Bridge Multilevel Inverter
title_sort Simplified Small-Signal Model for Output Voltage Control of Asymmetric Cascaded H-Bridge Multilevel Inverter
author Curi Busarello, Tiago Davi
author_facet Curi Busarello, Tiago Davi
Mortezaei, Ali
Morales Paredes, Helmo Kelis [UNESP]
Al-Durra, Ahmed
Pomilio, Jose Antenor
Simoes, Marcelo Godoy
author_role author
author2 Mortezaei, Ali
Morales Paredes, Helmo Kelis [UNESP]
Al-Durra, Ahmed
Pomilio, Jose Antenor
Simoes, Marcelo Godoy
author2_role author
author
author
author
author
dc.contributor.none.fl_str_mv Universidade Federal de Santa Catarina (UFSC)
Colorado Sch Mines
Universidade Estadual Paulista (Unesp)
Khalifa Univ Sci & Technol
Universidade Estadual de Campinas (UNICAMP)
dc.contributor.author.fl_str_mv Curi Busarello, Tiago Davi
Mortezaei, Ali
Morales Paredes, Helmo Kelis [UNESP]
Al-Durra, Ahmed
Pomilio, Jose Antenor
Simoes, Marcelo Godoy
dc.subject.por.fl_str_mv Modeling
multilevel inverter
small-signal
stair-case modulation
voltage control
topic Modeling
multilevel inverter
small-signal
stair-case modulation
voltage control
description This paper proposes a simplified small-signal model for output voltage control of a single-phase asymmetrical cascaded H-bridge multilevel inverter (ACHMI). The ACHMI is an n-series connected H-bridge converter, each one with a unique value at the dc link and usually scaled at {1:2:6:...} or {1:3:9:...}. By assuming that the small-signal variation component is equal in all n converter terminal ports, a simplified small-signal model is obtained. This assumption is carefully described and justified. To verify the veracity of the proposed model, two distinct control strategies are applied. One is a single-loop control scheme based on a modified proportional-integral (PI) controller. The other one is a double-loop control scheme based on a PI controller with feedforward action of the load current. Both controllers are tuned based on the dynamic behavior of the proposed model. Since the designed controllers based on the simplified model make the ACHMI output voltage to follow the reference without steady-state error, the proposed simplified model truly represents the inverter. Experimental results show the efficacy of the simplified model of the ACHMI through the two mentioned control strategies as well as the ACHMI installed in a microgrid.
publishDate 2018
dc.date.none.fl_str_mv 2018-11-29T05:57:15Z
2018-11-29T05:57:15Z
2018-04-01
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/article
format article
status_str publishedVersion
dc.identifier.uri.fl_str_mv http://dx.doi.org/10.1109/TPEL.2017.2704919
Ieee Transactions On Power Electronics. Piscataway: Ieee-inst Electrical Electronics Engineers Inc, v. 33, n. 4, p. 3509-3519, 2018.
0885-8993
http://hdl.handle.net/11449/165968
10.1109/TPEL.2017.2704919
WOS:000422933400065
WOS000422933400065.pdf
url http://dx.doi.org/10.1109/TPEL.2017.2704919
http://hdl.handle.net/11449/165968
identifier_str_mv Ieee Transactions On Power Electronics. Piscataway: Ieee-inst Electrical Electronics Engineers Inc, v. 33, n. 4, p. 3509-3519, 2018.
0885-8993
10.1109/TPEL.2017.2704919
WOS:000422933400065
WOS000422933400065.pdf
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv Ieee Transactions On Power Electronics
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv 3509-3519
application/pdf
dc.publisher.none.fl_str_mv Ieee-inst Electrical Electronics Engineers Inc
publisher.none.fl_str_mv Ieee-inst Electrical Electronics Engineers Inc
dc.source.none.fl_str_mv Web of Science
reponame:Repositório Institucional da UNESP
instname:Universidade Estadual Paulista (UNESP)
instacron:UNESP
instname_str Universidade Estadual Paulista (UNESP)
instacron_str UNESP
institution UNESP
reponame_str Repositório Institucional da UNESP
collection Repositório Institucional da UNESP
repository.name.fl_str_mv Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)
repository.mail.fl_str_mv
_version_ 1803649588543881216