Real-time module for digital image processing developed on a FPGA

Detalhes bibliográficos
Autor(a) principal: Mertes, Jacqueline G.
Data de Publicação: 2013
Outros Autores: Marranghello, Norian [UNESP], Pereira, Aledir S. [UNESP]
Tipo de documento: Artigo de conferência
Idioma: eng
Título da fonte: Repositório Institucional da UNESP
Texto Completo: http://dx.doi.org/10.3182/20130925-3-CZ-3023.00072
http://hdl.handle.net/11449/232154
Resumo: Real-time processing emerged as an important component in the digital image processing area. The fast and convenient processing opens news possibilities, for example, configurable image processing modules in order to massive processing of images. With this purpose, this paper describes a colored digital image processing system. This system can configure a set of filters according to the prescriptions of a user, in order to adapt the system to the images to be treated. Six filters that perform the tasks of smoothing, edge detection, histogram equalization, color normalization and brightness normalization compose such a set. The system was described using System Verilog hardware description language, and implemented in an Altera FPGA. Due to its configurable characteristic, this system is capable of processing colored images for several applications such as agricultural and medical. © IFAC.
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spelling Real-time module for digital image processing developed on a FPGADesign systemsDigital circuitsDigital filtersImage processingReal-timeReal-time processing emerged as an important component in the digital image processing area. The fast and convenient processing opens news possibilities, for example, configurable image processing modules in order to massive processing of images. With this purpose, this paper describes a colored digital image processing system. This system can configure a set of filters according to the prescriptions of a user, in order to adapt the system to the images to be treated. Six filters that perform the tasks of smoothing, edge detection, histogram equalization, color normalization and brightness normalization compose such a set. The system was described using System Verilog hardware description language, and implemented in an Altera FPGA. Due to its configurable characteristic, this system is capable of processing colored images for several applications such as agricultural and medical. © IFAC.Instituto de Pesquisa Eldorado, Campinas, SP 13083-898Sao Paulo State University UNESP IBILCE, São José do Rio Preto, SP 15054-000Sao Paulo State University UNESP IBILCE, São José do Rio Preto, SP 15054-000Instituto de Pesquisa EldoradoUniversidade Estadual Paulista (UNESP)Mertes, Jacqueline G.Marranghello, Norian [UNESP]Pereira, Aledir S. [UNESP]2022-04-29T08:49:21Z2022-04-29T08:49:21Z2013-01-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject405-410http://dx.doi.org/10.3182/20130925-3-CZ-3023.00072IFAC Proceedings Volumes (IFAC-PapersOnline), v. 12, n. PART 1, p. 405-410, 2013.1474-6670http://hdl.handle.net/11449/23215410.3182/20130925-3-CZ-3023.000722-s2.0-84886716149Scopusreponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPengIFAC Proceedings Volumes (IFAC-PapersOnline)info:eu-repo/semantics/openAccess2022-04-29T08:49:21Zoai:repositorio.unesp.br:11449/232154Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-08-05T17:03:30.832853Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false
dc.title.none.fl_str_mv Real-time module for digital image processing developed on a FPGA
title Real-time module for digital image processing developed on a FPGA
spellingShingle Real-time module for digital image processing developed on a FPGA
Mertes, Jacqueline G.
Design systems
Digital circuits
Digital filters
Image processing
Real-time
title_short Real-time module for digital image processing developed on a FPGA
title_full Real-time module for digital image processing developed on a FPGA
title_fullStr Real-time module for digital image processing developed on a FPGA
title_full_unstemmed Real-time module for digital image processing developed on a FPGA
title_sort Real-time module for digital image processing developed on a FPGA
author Mertes, Jacqueline G.
author_facet Mertes, Jacqueline G.
Marranghello, Norian [UNESP]
Pereira, Aledir S. [UNESP]
author_role author
author2 Marranghello, Norian [UNESP]
Pereira, Aledir S. [UNESP]
author2_role author
author
dc.contributor.none.fl_str_mv Instituto de Pesquisa Eldorado
Universidade Estadual Paulista (UNESP)
dc.contributor.author.fl_str_mv Mertes, Jacqueline G.
Marranghello, Norian [UNESP]
Pereira, Aledir S. [UNESP]
dc.subject.por.fl_str_mv Design systems
Digital circuits
Digital filters
Image processing
Real-time
topic Design systems
Digital circuits
Digital filters
Image processing
Real-time
description Real-time processing emerged as an important component in the digital image processing area. The fast and convenient processing opens news possibilities, for example, configurable image processing modules in order to massive processing of images. With this purpose, this paper describes a colored digital image processing system. This system can configure a set of filters according to the prescriptions of a user, in order to adapt the system to the images to be treated. Six filters that perform the tasks of smoothing, edge detection, histogram equalization, color normalization and brightness normalization compose such a set. The system was described using System Verilog hardware description language, and implemented in an Altera FPGA. Due to its configurable characteristic, this system is capable of processing colored images for several applications such as agricultural and medical. © IFAC.
publishDate 2013
dc.date.none.fl_str_mv 2013-01-01
2022-04-29T08:49:21Z
2022-04-29T08:49:21Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/conferenceObject
format conferenceObject
status_str publishedVersion
dc.identifier.uri.fl_str_mv http://dx.doi.org/10.3182/20130925-3-CZ-3023.00072
IFAC Proceedings Volumes (IFAC-PapersOnline), v. 12, n. PART 1, p. 405-410, 2013.
1474-6670
http://hdl.handle.net/11449/232154
10.3182/20130925-3-CZ-3023.00072
2-s2.0-84886716149
url http://dx.doi.org/10.3182/20130925-3-CZ-3023.00072
http://hdl.handle.net/11449/232154
identifier_str_mv IFAC Proceedings Volumes (IFAC-PapersOnline), v. 12, n. PART 1, p. 405-410, 2013.
1474-6670
10.3182/20130925-3-CZ-3023.00072
2-s2.0-84886716149
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv IFAC Proceedings Volumes (IFAC-PapersOnline)
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv 405-410
dc.source.none.fl_str_mv Scopus
reponame:Repositório Institucional da UNESP
instname:Universidade Estadual Paulista (UNESP)
instacron:UNESP
instname_str Universidade Estadual Paulista (UNESP)
instacron_str UNESP
institution UNESP
reponame_str Repositório Institucional da UNESP
collection Repositório Institucional da UNESP
repository.name.fl_str_mv Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)
repository.mail.fl_str_mv
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