FGSCM: A Fine-Grained Approach to Transactional Lock Elision

Detalhes bibliográficos
Autor(a) principal: Sousa, Gustavo [UNESP]
Data de Publicação: 2017
Outros Autores: Baldassin, Alexandro [UNESP]
Tipo de documento: Artigo de conferência
Idioma: eng
Título da fonte: Repositório Institucional da UNESP
Texto Completo: http://dx.doi.org/10.1109/SBAC-PAD.2017.22
http://hdl.handle.net/11449/170591
Resumo: Speculative Lock Elision (SLE) is a technique that allows critical sections to be executed optimistically by eliding the lock operation and enabling multiple threads to execute concurrently. In case of inconsistencies, the hardware automatically rolls back the execution and pessimistically acquires the original lock during runtime. The decision to elide the lock in SLE is performed transparently at the microarchitecture level and, although being convenient, it may sometimes hurt performance. To avoid that case, researchers have investigated Transactional Lock Elision (TLE), in which software-controlled hardware transactions are used instead, allowing the creation of policies and heuristics to manage lock elision. Typical implementations of TLE make use of a single lock to serialize the execution in case the original lock cannot be elided, which can potentially degrade performance. In order to improve on such cases, this paper proposes the Fine-Grained Software-assisted Conflict Management (FGSCM) scheme, a TLE technique that employs multiple locks so as to avoid unnecessary serialization of the code. The main idea of FGSCM is that not all threads that conflict inside a critical section are acessing the same region of shared memory. By automatically assigning distinct locks to these threads according to the memory section they access, the level of concurrency can be increased. In this paper we formalize FGSCM and provide an in-depth performance evaluation using a microbenchmark to stress several conflict behaviors. Our initial results with a prototype implementation using Intels Restricted Transactional Memory (RTM) are encouraging. With a quadcore machine, we observed an average performance gain of 11% compared to the single-auxiliary-lock SCM and 36% compared to a standard lock scheme, both for typical read-dominated workloads.
id UNSP_5379a390eee9ebeadcd4936092f20091
oai_identifier_str oai:repositorio.unesp.br:11449/170591
network_acronym_str UNSP
network_name_str Repositório Institucional da UNESP
repository_id_str 2946
spelling FGSCM: A Fine-Grained Approach to Transactional Lock ElisionHardware transactional memoryLock elisionLock removalParallel programmingTransactional lock elisionSpeculative Lock Elision (SLE) is a technique that allows critical sections to be executed optimistically by eliding the lock operation and enabling multiple threads to execute concurrently. In case of inconsistencies, the hardware automatically rolls back the execution and pessimistically acquires the original lock during runtime. The decision to elide the lock in SLE is performed transparently at the microarchitecture level and, although being convenient, it may sometimes hurt performance. To avoid that case, researchers have investigated Transactional Lock Elision (TLE), in which software-controlled hardware transactions are used instead, allowing the creation of policies and heuristics to manage lock elision. Typical implementations of TLE make use of a single lock to serialize the execution in case the original lock cannot be elided, which can potentially degrade performance. In order to improve on such cases, this paper proposes the Fine-Grained Software-assisted Conflict Management (FGSCM) scheme, a TLE technique that employs multiple locks so as to avoid unnecessary serialization of the code. The main idea of FGSCM is that not all threads that conflict inside a critical section are acessing the same region of shared memory. By automatically assigning distinct locks to these threads according to the memory section they access, the level of concurrency can be increased. In this paper we formalize FGSCM and provide an in-depth performance evaluation using a microbenchmark to stress several conflict behaviors. Our initial results with a prototype implementation using Intels Restricted Transactional Memory (RTM) are encouraging. With a quadcore machine, we observed an average performance gain of 11% compared to the single-auxiliary-lock SCM and 36% compared to a standard lock scheme, both for typical read-dominated workloads.Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)Univ Estadual Paulista - UNESPUniv Estadual Paulista - UNESPCNPq: 446160/2014-8Universidade Estadual Paulista (Unesp)Sousa, Gustavo [UNESP]Baldassin, Alexandro [UNESP]2018-12-11T16:51:36Z2018-12-11T16:51:36Z2017-11-08info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject113-120http://dx.doi.org/10.1109/SBAC-PAD.2017.22Proceedings - 29th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2017, p. 113-120.http://hdl.handle.net/11449/17059110.1109/SBAC-PAD.2017.222-s2.0-85041209433Scopusreponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPengProceedings - 29th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2017info:eu-repo/semantics/openAccess2021-10-23T21:46:59Zoai:repositorio.unesp.br:11449/170591Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-08-05T23:50:19.242491Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false
dc.title.none.fl_str_mv FGSCM: A Fine-Grained Approach to Transactional Lock Elision
title FGSCM: A Fine-Grained Approach to Transactional Lock Elision
spellingShingle FGSCM: A Fine-Grained Approach to Transactional Lock Elision
Sousa, Gustavo [UNESP]
Hardware transactional memory
Lock elision
Lock removal
Parallel programming
Transactional lock elision
title_short FGSCM: A Fine-Grained Approach to Transactional Lock Elision
title_full FGSCM: A Fine-Grained Approach to Transactional Lock Elision
title_fullStr FGSCM: A Fine-Grained Approach to Transactional Lock Elision
title_full_unstemmed FGSCM: A Fine-Grained Approach to Transactional Lock Elision
title_sort FGSCM: A Fine-Grained Approach to Transactional Lock Elision
author Sousa, Gustavo [UNESP]
author_facet Sousa, Gustavo [UNESP]
Baldassin, Alexandro [UNESP]
author_role author
author2 Baldassin, Alexandro [UNESP]
author2_role author
dc.contributor.none.fl_str_mv Universidade Estadual Paulista (Unesp)
dc.contributor.author.fl_str_mv Sousa, Gustavo [UNESP]
Baldassin, Alexandro [UNESP]
dc.subject.por.fl_str_mv Hardware transactional memory
Lock elision
Lock removal
Parallel programming
Transactional lock elision
topic Hardware transactional memory
Lock elision
Lock removal
Parallel programming
Transactional lock elision
description Speculative Lock Elision (SLE) is a technique that allows critical sections to be executed optimistically by eliding the lock operation and enabling multiple threads to execute concurrently. In case of inconsistencies, the hardware automatically rolls back the execution and pessimistically acquires the original lock during runtime. The decision to elide the lock in SLE is performed transparently at the microarchitecture level and, although being convenient, it may sometimes hurt performance. To avoid that case, researchers have investigated Transactional Lock Elision (TLE), in which software-controlled hardware transactions are used instead, allowing the creation of policies and heuristics to manage lock elision. Typical implementations of TLE make use of a single lock to serialize the execution in case the original lock cannot be elided, which can potentially degrade performance. In order to improve on such cases, this paper proposes the Fine-Grained Software-assisted Conflict Management (FGSCM) scheme, a TLE technique that employs multiple locks so as to avoid unnecessary serialization of the code. The main idea of FGSCM is that not all threads that conflict inside a critical section are acessing the same region of shared memory. By automatically assigning distinct locks to these threads according to the memory section they access, the level of concurrency can be increased. In this paper we formalize FGSCM and provide an in-depth performance evaluation using a microbenchmark to stress several conflict behaviors. Our initial results with a prototype implementation using Intels Restricted Transactional Memory (RTM) are encouraging. With a quadcore machine, we observed an average performance gain of 11% compared to the single-auxiliary-lock SCM and 36% compared to a standard lock scheme, both for typical read-dominated workloads.
publishDate 2017
dc.date.none.fl_str_mv 2017-11-08
2018-12-11T16:51:36Z
2018-12-11T16:51:36Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/conferenceObject
format conferenceObject
status_str publishedVersion
dc.identifier.uri.fl_str_mv http://dx.doi.org/10.1109/SBAC-PAD.2017.22
Proceedings - 29th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2017, p. 113-120.
http://hdl.handle.net/11449/170591
10.1109/SBAC-PAD.2017.22
2-s2.0-85041209433
url http://dx.doi.org/10.1109/SBAC-PAD.2017.22
http://hdl.handle.net/11449/170591
identifier_str_mv Proceedings - 29th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2017, p. 113-120.
10.1109/SBAC-PAD.2017.22
2-s2.0-85041209433
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv Proceedings - 29th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2017
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv 113-120
dc.source.none.fl_str_mv Scopus
reponame:Repositório Institucional da UNESP
instname:Universidade Estadual Paulista (UNESP)
instacron:UNESP
instname_str Universidade Estadual Paulista (UNESP)
instacron_str UNESP
institution UNESP
reponame_str Repositório Institucional da UNESP
collection Repositório Institucional da UNESP
repository.name.fl_str_mv Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)
repository.mail.fl_str_mv
_version_ 1808129557916549120