On the algebraic reuse of hardware design
Autor(a) principal: | |
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Data de Publicação: | 1998 |
Outros Autores: | |
Tipo de documento: | Artigo de conferência |
Idioma: | eng |
Título da fonte: | Repositório Institucional da UNESP |
Texto Completo: | http://hdl.handle.net/11449/194536 |
Resumo: | The widespread use of computers in a diversity of activities today demands complex computational systems to be produced efficiently. This factor has led to a requirement for new methods and techniques to enhance controllability, quality and productivity of systems. Reusability is recognized as a basic principle for enhancing productivity and quality of engineering products. Additionally, formal development of software/hardware has emerged as an approach to ensure quality and help handle the complexity of description of such systems. So, for reasons of economy, productivity, quality and time to market, it is highly desirable to formally reuse hardware/software components. This paper presents a foundation for formal reuse of synchronous processes using a process algebra (EPA [2]). Assuming the existence of a library of formally verified components, we propose to make effective reuse of these existing elements when creating new systems. The strategy used here is to formally create an interface element with which a library process is composed in order to implement the desired component. In doing so, the verification task of the whole system is reduced to verifying the interface element. |
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Repositório Institucional da UNESP |
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On the algebraic reuse of hardware designreusabilityhigh-level synthesisprocess algebrasbisimulationinterface equationThe widespread use of computers in a diversity of activities today demands complex computational systems to be produced efficiently. This factor has led to a requirement for new methods and techniques to enhance controllability, quality and productivity of systems. Reusability is recognized as a basic principle for enhancing productivity and quality of engineering products. Additionally, formal development of software/hardware has emerged as an approach to ensure quality and help handle the complexity of description of such systems. So, for reasons of economy, productivity, quality and time to market, it is highly desirable to formally reuse hardware/software components. This paper presents a foundation for formal reuse of synchronous processes using a process algebra (EPA [2]). Assuming the existence of a library of formally verified components, we propose to make effective reuse of these existing elements when creating new systems. The strategy used here is to formally create an interface element with which a library process is composed in order to implement the desired component. In doing so, the verification task of the whole system is reduced to verifying the interface element.State Univ Sao Paulo, USP, IME, Dept Comp Sci, BR-05508900 Sao Paulo, BrazilState Univ Sao Paulo, USP, IME, Dept Comp Sci, BR-05508900 Sao Paulo, BrazilIeeeUniversidade Estadual Paulista (Unesp)Melo, A. C. deIEEE2020-12-10T16:29:17Z2020-12-10T16:29:17Z1998-01-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObjectE306-E309Iscas '98 - Proceedings Of The 1998 International Symposium On Circuits And Systems, Vols 1-6. New York: Ieee, p. E306-E309, 1998.http://hdl.handle.net/11449/194536WOS:000075224600805Web of Sciencereponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPengIscas '98 - Proceedings Of The 1998 International Symposium On Circuits And Systems, Vols 1-6info:eu-repo/semantics/openAccess2021-10-22T17:11:50Zoai:repositorio.unesp.br:11449/194536Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462021-10-22T17:11:50Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false |
dc.title.none.fl_str_mv |
On the algebraic reuse of hardware design |
title |
On the algebraic reuse of hardware design |
spellingShingle |
On the algebraic reuse of hardware design Melo, A. C. de reusability high-level synthesis process algebras bisimulation interface equation |
title_short |
On the algebraic reuse of hardware design |
title_full |
On the algebraic reuse of hardware design |
title_fullStr |
On the algebraic reuse of hardware design |
title_full_unstemmed |
On the algebraic reuse of hardware design |
title_sort |
On the algebraic reuse of hardware design |
author |
Melo, A. C. de |
author_facet |
Melo, A. C. de IEEE |
author_role |
author |
author2 |
IEEE |
author2_role |
author |
dc.contributor.none.fl_str_mv |
Universidade Estadual Paulista (Unesp) |
dc.contributor.author.fl_str_mv |
Melo, A. C. de IEEE |
dc.subject.por.fl_str_mv |
reusability high-level synthesis process algebras bisimulation interface equation |
topic |
reusability high-level synthesis process algebras bisimulation interface equation |
description |
The widespread use of computers in a diversity of activities today demands complex computational systems to be produced efficiently. This factor has led to a requirement for new methods and techniques to enhance controllability, quality and productivity of systems. Reusability is recognized as a basic principle for enhancing productivity and quality of engineering products. Additionally, formal development of software/hardware has emerged as an approach to ensure quality and help handle the complexity of description of such systems. So, for reasons of economy, productivity, quality and time to market, it is highly desirable to formally reuse hardware/software components. This paper presents a foundation for formal reuse of synchronous processes using a process algebra (EPA [2]). Assuming the existence of a library of formally verified components, we propose to make effective reuse of these existing elements when creating new systems. The strategy used here is to formally create an interface element with which a library process is composed in order to implement the desired component. In doing so, the verification task of the whole system is reduced to verifying the interface element. |
publishDate |
1998 |
dc.date.none.fl_str_mv |
1998-01-01 2020-12-10T16:29:17Z 2020-12-10T16:29:17Z |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/conferenceObject |
format |
conferenceObject |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
Iscas '98 - Proceedings Of The 1998 International Symposium On Circuits And Systems, Vols 1-6. New York: Ieee, p. E306-E309, 1998. http://hdl.handle.net/11449/194536 WOS:000075224600805 |
identifier_str_mv |
Iscas '98 - Proceedings Of The 1998 International Symposium On Circuits And Systems, Vols 1-6. New York: Ieee, p. E306-E309, 1998. WOS:000075224600805 |
url |
http://hdl.handle.net/11449/194536 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.none.fl_str_mv |
Iscas '98 - Proceedings Of The 1998 International Symposium On Circuits And Systems, Vols 1-6 |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.format.none.fl_str_mv |
E306-E309 |
dc.publisher.none.fl_str_mv |
Ieee |
publisher.none.fl_str_mv |
Ieee |
dc.source.none.fl_str_mv |
Web of Science reponame:Repositório Institucional da UNESP instname:Universidade Estadual Paulista (UNESP) instacron:UNESP |
instname_str |
Universidade Estadual Paulista (UNESP) |
instacron_str |
UNESP |
institution |
UNESP |
reponame_str |
Repositório Institucional da UNESP |
collection |
Repositório Institucional da UNESP |
repository.name.fl_str_mv |
Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP) |
repository.mail.fl_str_mv |
|
_version_ |
1799964532535197696 |