Improving Speculative taskloop in Hardware Transactional Memory

Detalhes bibliográficos
Autor(a) principal: Salamanca, Juan [UNESP]
Data de Publicação: 2021
Outros Autores: Baldassin, Alexandro [UNESP]
Tipo de documento: Artigo de conferência
Idioma: eng
Título da fonte: Repositório Institucional da UNESP
Texto Completo: http://dx.doi.org/10.1007/978-3-030-85262-7_1
http://hdl.handle.net/11449/222470
Resumo: Previous work proposed and evaluated Speculative taskloop (STL) on Intel Core implementing new clauses and constructs in OpenMP. The results indicated that, despite achieving some speed-ups, there was a phenomenon called the Lost-Thread Effect that caused the performance degradation of STL parallelization. This issue is caused by the nonmonotonic scheduling implemented in the LLVM OpenMP Runtime Library. This paper presents an improvement in the STL mechanism by modifying the OpenMP runtime to allow monotonic scheduling of tasks generated by taskloop. We perform an evaluation with two different versions of the OpenMP runtime, both optimized for STL revealing that, for certain loops, infinite slowdowns (deadlocks) using the original OpenMP runtime can be transformed in speed-ups by applying monotonic scheduling. The experimental results show the performance improvement of STL using the modified version of the runtime, reaching speed-ups of up to 2.18 ×.
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spelling Improving Speculative taskloop in Hardware Transactional MemoryOpenMPSpeculative parallelizationtaskloopPrevious work proposed and evaluated Speculative taskloop (STL) on Intel Core implementing new clauses and constructs in OpenMP. The results indicated that, despite achieving some speed-ups, there was a phenomenon called the Lost-Thread Effect that caused the performance degradation of STL parallelization. This issue is caused by the nonmonotonic scheduling implemented in the LLVM OpenMP Runtime Library. This paper presents an improvement in the STL mechanism by modifying the OpenMP runtime to allow monotonic scheduling of tasks generated by taskloop. We perform an evaluation with two different versions of the OpenMP runtime, both optimized for STL revealing that, for certain loops, infinite slowdowns (deadlocks) using the original OpenMP runtime can be transformed in speed-ups by applying monotonic scheduling. The experimental results show the performance improvement of STL using the modified version of the runtime, reaching speed-ups of up to 2.18 ×.IGCE – Sao Paulo State University (Unesp)IGCE – Sao Paulo State University (Unesp)Universidade Estadual Paulista (UNESP)Salamanca, Juan [UNESP]Baldassin, Alexandro [UNESP]2022-04-28T19:44:50Z2022-04-28T19:44:50Z2021-01-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject3-17http://dx.doi.org/10.1007/978-3-030-85262-7_1Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), v. 12870 LNCS, p. 3-17.1611-33490302-9743http://hdl.handle.net/11449/22247010.1007/978-3-030-85262-7_12-s2.0-85115447282Scopusreponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPengLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)info:eu-repo/semantics/openAccess2022-04-28T19:44:50Zoai:repositorio.unesp.br:11449/222470Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-08-05T19:15:44.792614Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false
dc.title.none.fl_str_mv Improving Speculative taskloop in Hardware Transactional Memory
title Improving Speculative taskloop in Hardware Transactional Memory
spellingShingle Improving Speculative taskloop in Hardware Transactional Memory
Salamanca, Juan [UNESP]
OpenMP
Speculative parallelization
taskloop
title_short Improving Speculative taskloop in Hardware Transactional Memory
title_full Improving Speculative taskloop in Hardware Transactional Memory
title_fullStr Improving Speculative taskloop in Hardware Transactional Memory
title_full_unstemmed Improving Speculative taskloop in Hardware Transactional Memory
title_sort Improving Speculative taskloop in Hardware Transactional Memory
author Salamanca, Juan [UNESP]
author_facet Salamanca, Juan [UNESP]
Baldassin, Alexandro [UNESP]
author_role author
author2 Baldassin, Alexandro [UNESP]
author2_role author
dc.contributor.none.fl_str_mv Universidade Estadual Paulista (UNESP)
dc.contributor.author.fl_str_mv Salamanca, Juan [UNESP]
Baldassin, Alexandro [UNESP]
dc.subject.por.fl_str_mv OpenMP
Speculative parallelization
taskloop
topic OpenMP
Speculative parallelization
taskloop
description Previous work proposed and evaluated Speculative taskloop (STL) on Intel Core implementing new clauses and constructs in OpenMP. The results indicated that, despite achieving some speed-ups, there was a phenomenon called the Lost-Thread Effect that caused the performance degradation of STL parallelization. This issue is caused by the nonmonotonic scheduling implemented in the LLVM OpenMP Runtime Library. This paper presents an improvement in the STL mechanism by modifying the OpenMP runtime to allow monotonic scheduling of tasks generated by taskloop. We perform an evaluation with two different versions of the OpenMP runtime, both optimized for STL revealing that, for certain loops, infinite slowdowns (deadlocks) using the original OpenMP runtime can be transformed in speed-ups by applying monotonic scheduling. The experimental results show the performance improvement of STL using the modified version of the runtime, reaching speed-ups of up to 2.18 ×.
publishDate 2021
dc.date.none.fl_str_mv 2021-01-01
2022-04-28T19:44:50Z
2022-04-28T19:44:50Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/conferenceObject
format conferenceObject
status_str publishedVersion
dc.identifier.uri.fl_str_mv http://dx.doi.org/10.1007/978-3-030-85262-7_1
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), v. 12870 LNCS, p. 3-17.
1611-3349
0302-9743
http://hdl.handle.net/11449/222470
10.1007/978-3-030-85262-7_1
2-s2.0-85115447282
url http://dx.doi.org/10.1007/978-3-030-85262-7_1
http://hdl.handle.net/11449/222470
identifier_str_mv Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), v. 12870 LNCS, p. 3-17.
1611-3349
0302-9743
10.1007/978-3-030-85262-7_1
2-s2.0-85115447282
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv 3-17
dc.source.none.fl_str_mv Scopus
reponame:Repositório Institucional da UNESP
instname:Universidade Estadual Paulista (UNESP)
instacron:UNESP
instname_str Universidade Estadual Paulista (UNESP)
instacron_str UNESP
institution UNESP
reponame_str Repositório Institucional da UNESP
collection Repositório Institucional da UNESP
repository.name.fl_str_mv Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)
repository.mail.fl_str_mv
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