Horizontal, Stacked or Vertical Silicon Nanowires: Does it Matter from a Low-Frequency Noise Perspective?

• Autor(a) principal: Simoen, Eddy
• Data de Publicação: 2020
• Outros Autores: Oliveira, Alberto Vinicius de, Der Agopian, Paula Ghedini [UNESP], Ritzenthaler, Romain, Mertens, Hans, Horiguchi, Naoto, Martino, Joao Antonio, Claeys, Cor, Veloso, Anabela, IEEE
• Tipo de documento: Artigo de conferência
• Idioma: eng
• Título da fonte: Repositório Institucional da UNESP
• Texto Completo: http://dx.doi.org/10.1109/EUROSOI-ULIS49407.2020.9365338; http://hdl.handle.net/11449/237551
• topic: Gate-All-Around; Nanowires; Nanosheets; Low-frequency noise

This work reviews the low-frequency noise performance of different flavors of silicon Gate-All-Around Nanowire (NW) (or Nanosheet - NS) transistors. For the horizontal devices, the 1/f-like noise is dominated by the number fluctuations mechanism, so that the Power Spectral Density (PSD) is directly proportional with the trap density in the gate stack. The impact of different process options and device architectures (junctionless versus inversion mode) is discussed. Overall, it is found that the average 1/f noise PSD is reducing going from single NW transistors on Silicon-on-Insulator substrates, to stacked horizontal NS devices and, finally, vertical NW FETs. In the latter case, white noise may dominate the lowfrequency noise spectrum.