Finding optimal qubit permutations for IBM's quantum computer architectures

Detalhes bibliográficos
Autor(a) principal: De Almeida, Alexandre A.A. [UNESP]
Data de Publicação: 2019
Outros Autores: Dueck, Gerhard W., Da Silva, Alexandre C.R. [UNESP]
Tipo de documento: Artigo de conferência
Idioma: eng
Título da fonte: Repositório Institucional da UNESP
Texto Completo: http://dx.doi.org/10.1145/3338852.3339829
http://hdl.handle.net/11449/198019
Resumo: IBM offers quantum processors for Clifford+T circuits. The only restriction is that not all CNOT gates are implemented and must be substituted with alternate sequences of gates. Each CNOT has its own mapping with a respective cost. However, by permuting the qubits, the number of CNOT that need mappings can be reduced. The problem is to find a good permutation without an exhaustive search. In this paperwe propose a solution for this problem. The permutation problem is formulated as an Integer Linear Programming (ILP) problem. Solving the ILP problem, the lowest cost permutation for the CNOT mappings is guaranteed. To test and validated the proposed formulation, quantum architectures with 5 and 16 qubits were used. The ILP formulation along with mapping techniques found circuits with up to 64% fewer gates than other approaches.
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spelling Finding optimal qubit permutations for IBM's quantum computer architecturesIBM quantum processorsInteger Linear ProgrammingQuantum circuitIBM offers quantum processors for Clifford+T circuits. The only restriction is that not all CNOT gates are implemented and must be substituted with alternate sequences of gates. Each CNOT has its own mapping with a respective cost. However, by permuting the qubits, the number of CNOT that need mappings can be reduced. The problem is to find a good permutation without an exhaustive search. In this paperwe propose a solution for this problem. The permutation problem is formulated as an Integer Linear Programming (ILP) problem. Solving the ILP problem, the lowest cost permutation for the CNOT mappings is guaranteed. To test and validated the proposed formulation, quantum architectures with 5 and 16 qubits were used. The ILP formulation along with mapping techniques found circuits with up to 64% fewer gates than other approaches.School of Engineering São Paulo State University (Unesp)Faculty of Computer Science University of New BrunswickSchool of Engineering São Paulo State University (Unesp)Universidade Estadual Paulista (Unesp)University of New BrunswickDe Almeida, Alexandre A.A. [UNESP]Dueck, Gerhard W.Da Silva, Alexandre C.R. [UNESP]2020-12-12T00:56:46Z2020-12-12T00:56:46Z2019-08-26info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObjecthttp://dx.doi.org/10.1145/3338852.3339829Proceedings - 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019.http://hdl.handle.net/11449/19801910.1145/3338852.33398292-s2.0-85073465140Scopusreponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPengProceedings - 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019info:eu-repo/semantics/openAccess2021-10-23T07:21:22Zoai:repositorio.unesp.br:11449/198019Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-08-05T15:05:07.204402Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false
dc.title.none.fl_str_mv Finding optimal qubit permutations for IBM's quantum computer architectures
title Finding optimal qubit permutations for IBM's quantum computer architectures
spellingShingle Finding optimal qubit permutations for IBM's quantum computer architectures
De Almeida, Alexandre A.A. [UNESP]
IBM quantum processors
Integer Linear Programming
Quantum circuit
title_short Finding optimal qubit permutations for IBM's quantum computer architectures
title_full Finding optimal qubit permutations for IBM's quantum computer architectures
title_fullStr Finding optimal qubit permutations for IBM's quantum computer architectures
title_full_unstemmed Finding optimal qubit permutations for IBM's quantum computer architectures
title_sort Finding optimal qubit permutations for IBM's quantum computer architectures
author De Almeida, Alexandre A.A. [UNESP]
author_facet De Almeida, Alexandre A.A. [UNESP]
Dueck, Gerhard W.
Da Silva, Alexandre C.R. [UNESP]
author_role author
author2 Dueck, Gerhard W.
Da Silva, Alexandre C.R. [UNESP]
author2_role author
author
dc.contributor.none.fl_str_mv Universidade Estadual Paulista (Unesp)
University of New Brunswick
dc.contributor.author.fl_str_mv De Almeida, Alexandre A.A. [UNESP]
Dueck, Gerhard W.
Da Silva, Alexandre C.R. [UNESP]
dc.subject.por.fl_str_mv IBM quantum processors
Integer Linear Programming
Quantum circuit
topic IBM quantum processors
Integer Linear Programming
Quantum circuit
description IBM offers quantum processors for Clifford+T circuits. The only restriction is that not all CNOT gates are implemented and must be substituted with alternate sequences of gates. Each CNOT has its own mapping with a respective cost. However, by permuting the qubits, the number of CNOT that need mappings can be reduced. The problem is to find a good permutation without an exhaustive search. In this paperwe propose a solution for this problem. The permutation problem is formulated as an Integer Linear Programming (ILP) problem. Solving the ILP problem, the lowest cost permutation for the CNOT mappings is guaranteed. To test and validated the proposed formulation, quantum architectures with 5 and 16 qubits were used. The ILP formulation along with mapping techniques found circuits with up to 64% fewer gates than other approaches.
publishDate 2019
dc.date.none.fl_str_mv 2019-08-26
2020-12-12T00:56:46Z
2020-12-12T00:56:46Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/conferenceObject
format conferenceObject
status_str publishedVersion
dc.identifier.uri.fl_str_mv http://dx.doi.org/10.1145/3338852.3339829
Proceedings - 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019.
http://hdl.handle.net/11449/198019
10.1145/3338852.3339829
2-s2.0-85073465140
url http://dx.doi.org/10.1145/3338852.3339829
http://hdl.handle.net/11449/198019
identifier_str_mv Proceedings - 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019.
10.1145/3338852.3339829
2-s2.0-85073465140
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv Proceedings - 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.source.none.fl_str_mv Scopus
reponame:Repositório Institucional da UNESP
instname:Universidade Estadual Paulista (UNESP)
instacron:UNESP
instname_str Universidade Estadual Paulista (UNESP)
instacron_str UNESP
institution UNESP
reponame_str Repositório Institucional da UNESP
collection Repositório Institucional da UNESP
repository.name.fl_str_mv Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)
repository.mail.fl_str_mv
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