Template-based mapping of reversible circuits to IBM quantum computers
Autor(a) principal: | |
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Data de Publicação: | 2022 |
Outros Autores: | , , |
Tipo de documento: | Artigo |
Idioma: | eng |
Título da fonte: | Repositório Institucional da UNESP |
Texto Completo: | http://dx.doi.org/10.1016/j.micpro.2022.104487 http://hdl.handle.net/11449/223651 |
Resumo: | In order to make the most of the increasing computational power of recently developed quantum computers, it is crucial to perform an efficient mapping of a given quantum circuit that realizes the desired quantum algorithm to the targeted quantum computer (so-called technology mapping). In most cases, the limitations of the targeted quantum hardware have not been taken into account when generating these quantum circuits in the first place. Thus, the technology mapping is likely to induce a considerable overhead for such circuits in order prepare them for the execution on the actual device. In this work, we consider the realization of reversible circuits consisting of multiple-controlled Toffoli gates on IBM quantum computers. Using templates for the realization of the reversible/quantum gates allows to perform a topology-aware decomposition of MCT gates that exhibits the potential of significant reductions of the technology mapping overhead. |
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Template-based mapping of reversible circuits to IBM quantum computersNearest neighbor constraintsNISQ architecturesQuantum circuit optimizationQuantum computationIn order to make the most of the increasing computational power of recently developed quantum computers, it is crucial to perform an efficient mapping of a given quantum circuit that realizes the desired quantum algorithm to the targeted quantum computer (so-called technology mapping). In most cases, the limitations of the targeted quantum hardware have not been taken into account when generating these quantum circuits in the first place. Thus, the technology mapping is likely to induce a considerable overhead for such circuits in order prepare them for the execution on the actual device. In this work, we consider the realization of reversible circuits consisting of multiple-controlled Toffoli gates on IBM quantum computers. Using templates for the realization of the reversible/quantum gates allows to perform a topology-aware decomposition of MCT gates that exhibits the potential of significant reductions of the technology mapping overhead.Department of Computer Science University of BremenCyber-Physical Systems DFKI GmbHSchool of Engineering Ilha Solteira São Paulo State UniversityFaculty of Computer Science University of New BrunswickSchool of Engineering Ilha Solteira São Paulo State UniversityUniversity of BremenDFKI GmbHUniversidade Estadual Paulista (UNESP)University of New BrunswickNiemann, Philippde Almeida, Alexandre A.A. [UNESP]Dueck, GerhardDrechsler, Rolf2022-04-28T19:51:58Z2022-04-28T19:51:58Z2022-04-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articlehttp://dx.doi.org/10.1016/j.micpro.2022.104487Microprocessors and Microsystems, v. 90.0141-9331http://hdl.handle.net/11449/22365110.1016/j.micpro.2022.1044872-s2.0-85126395629Scopusreponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPengMicroprocessors and Microsystemsinfo:eu-repo/semantics/openAccess2022-04-28T19:51:58Zoai:repositorio.unesp.br:11449/223651Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-08-05T16:32:02.139369Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false |
dc.title.none.fl_str_mv |
Template-based mapping of reversible circuits to IBM quantum computers |
title |
Template-based mapping of reversible circuits to IBM quantum computers |
spellingShingle |
Template-based mapping of reversible circuits to IBM quantum computers Niemann, Philipp Nearest neighbor constraints NISQ architectures Quantum circuit optimization Quantum computation |
title_short |
Template-based mapping of reversible circuits to IBM quantum computers |
title_full |
Template-based mapping of reversible circuits to IBM quantum computers |
title_fullStr |
Template-based mapping of reversible circuits to IBM quantum computers |
title_full_unstemmed |
Template-based mapping of reversible circuits to IBM quantum computers |
title_sort |
Template-based mapping of reversible circuits to IBM quantum computers |
author |
Niemann, Philipp |
author_facet |
Niemann, Philipp de Almeida, Alexandre A.A. [UNESP] Dueck, Gerhard Drechsler, Rolf |
author_role |
author |
author2 |
de Almeida, Alexandre A.A. [UNESP] Dueck, Gerhard Drechsler, Rolf |
author2_role |
author author author |
dc.contributor.none.fl_str_mv |
University of Bremen DFKI GmbH Universidade Estadual Paulista (UNESP) University of New Brunswick |
dc.contributor.author.fl_str_mv |
Niemann, Philipp de Almeida, Alexandre A.A. [UNESP] Dueck, Gerhard Drechsler, Rolf |
dc.subject.por.fl_str_mv |
Nearest neighbor constraints NISQ architectures Quantum circuit optimization Quantum computation |
topic |
Nearest neighbor constraints NISQ architectures Quantum circuit optimization Quantum computation |
description |
In order to make the most of the increasing computational power of recently developed quantum computers, it is crucial to perform an efficient mapping of a given quantum circuit that realizes the desired quantum algorithm to the targeted quantum computer (so-called technology mapping). In most cases, the limitations of the targeted quantum hardware have not been taken into account when generating these quantum circuits in the first place. Thus, the technology mapping is likely to induce a considerable overhead for such circuits in order prepare them for the execution on the actual device. In this work, we consider the realization of reversible circuits consisting of multiple-controlled Toffoli gates on IBM quantum computers. Using templates for the realization of the reversible/quantum gates allows to perform a topology-aware decomposition of MCT gates that exhibits the potential of significant reductions of the technology mapping overhead. |
publishDate |
2022 |
dc.date.none.fl_str_mv |
2022-04-28T19:51:58Z 2022-04-28T19:51:58Z 2022-04-01 |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/article |
format |
article |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://dx.doi.org/10.1016/j.micpro.2022.104487 Microprocessors and Microsystems, v. 90. 0141-9331 http://hdl.handle.net/11449/223651 10.1016/j.micpro.2022.104487 2-s2.0-85126395629 |
url |
http://dx.doi.org/10.1016/j.micpro.2022.104487 http://hdl.handle.net/11449/223651 |
identifier_str_mv |
Microprocessors and Microsystems, v. 90. 0141-9331 10.1016/j.micpro.2022.104487 2-s2.0-85126395629 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.none.fl_str_mv |
Microprocessors and Microsystems |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.source.none.fl_str_mv |
Scopus reponame:Repositório Institucional da UNESP instname:Universidade Estadual Paulista (UNESP) instacron:UNESP |
instname_str |
Universidade Estadual Paulista (UNESP) |
instacron_str |
UNESP |
institution |
UNESP |
reponame_str |
Repositório Institucional da UNESP |
collection |
Repositório Institucional da UNESP |
repository.name.fl_str_mv |
Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP) |
repository.mail.fl_str_mv |
|
_version_ |
1808128668288942080 |