An algorithmic of analog-to-digital converter using current-mode and digital CMOS process

Detalhes bibliográficos
Autor(a) principal: Oki, N.
Data de Publicação: 1999
Tipo de documento: Artigo de conferência
Idioma: eng
Título da fonte: Repositório Institucional da UNESP
Texto Completo: http://dx.doi.org/10.1109/MWSCAS.1998.759544
http://hdl.handle.net/11449/9725
Resumo: In this paper a new algorithmic of Analog-to-Digital Converter is presented. This new topology use the current-mode technique that allows a large dynamic range and can be implemented in digital CMOS process. The ADC proposed is very small and can handle high sampling rates. Simulation results using a 1.2um CMOS process show that an 8-b ADC can support a sampling rate of 50MHz.
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spelling An algorithmic of analog-to-digital converter using current-mode and digital CMOS processIn this paper a new algorithmic of Analog-to-Digital Converter is presented. This new topology use the current-mode technique that allows a large dynamic range and can be implemented in digital CMOS process. The ADC proposed is very small and can handle high sampling rates. Simulation results using a 1.2um CMOS process show that an 8-b ADC can support a sampling rate of 50MHz.UNESP, FEIS, DEE, São Paulo, BrazilUNESP, FEIS, DEE, São Paulo, BrazilIEEE Computer SocUniversidade Estadual Paulista (Unesp)Oki, N.2014-05-20T13:29:01Z2014-05-20T13:29:01Z1999-01-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject520-521http://dx.doi.org/10.1109/MWSCAS.1998.7595441998 Midwest Symposium on Circuits and Systems, Proceedings. Los Alamitos: IEEE Computer Soc, p. 520-521, 1999.http://hdl.handle.net/11449/972510.1109/MWSCAS.1998.759544WOS:0000795632001201525717947689076Web of Sciencereponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPeng1998 Midwest Symposium on Circuits and Systems, Proceedingsinfo:eu-repo/semantics/openAccess2024-07-04T19:11:44Zoai:repositorio.unesp.br:11449/9725Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-08-05T19:33:21.442621Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false
dc.title.none.fl_str_mv An algorithmic of analog-to-digital converter using current-mode and digital CMOS process
title An algorithmic of analog-to-digital converter using current-mode and digital CMOS process
spellingShingle An algorithmic of analog-to-digital converter using current-mode and digital CMOS process
Oki, N.
title_short An algorithmic of analog-to-digital converter using current-mode and digital CMOS process
title_full An algorithmic of analog-to-digital converter using current-mode and digital CMOS process
title_fullStr An algorithmic of analog-to-digital converter using current-mode and digital CMOS process
title_full_unstemmed An algorithmic of analog-to-digital converter using current-mode and digital CMOS process
title_sort An algorithmic of analog-to-digital converter using current-mode and digital CMOS process
author Oki, N.
author_facet Oki, N.
author_role author
dc.contributor.none.fl_str_mv Universidade Estadual Paulista (Unesp)
dc.contributor.author.fl_str_mv Oki, N.
description In this paper a new algorithmic of Analog-to-Digital Converter is presented. This new topology use the current-mode technique that allows a large dynamic range and can be implemented in digital CMOS process. The ADC proposed is very small and can handle high sampling rates. Simulation results using a 1.2um CMOS process show that an 8-b ADC can support a sampling rate of 50MHz.
publishDate 1999
dc.date.none.fl_str_mv 1999-01-01
2014-05-20T13:29:01Z
2014-05-20T13:29:01Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/conferenceObject
format conferenceObject
status_str publishedVersion
dc.identifier.uri.fl_str_mv http://dx.doi.org/10.1109/MWSCAS.1998.759544
1998 Midwest Symposium on Circuits and Systems, Proceedings. Los Alamitos: IEEE Computer Soc, p. 520-521, 1999.
http://hdl.handle.net/11449/9725
10.1109/MWSCAS.1998.759544
WOS:000079563200120
1525717947689076
url http://dx.doi.org/10.1109/MWSCAS.1998.759544
http://hdl.handle.net/11449/9725
identifier_str_mv 1998 Midwest Symposium on Circuits and Systems, Proceedings. Los Alamitos: IEEE Computer Soc, p. 520-521, 1999.
10.1109/MWSCAS.1998.759544
WOS:000079563200120
1525717947689076
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv 1998 Midwest Symposium on Circuits and Systems, Proceedings
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv 520-521
dc.publisher.none.fl_str_mv IEEE Computer Soc
publisher.none.fl_str_mv IEEE Computer Soc
dc.source.none.fl_str_mv Web of Science
reponame:Repositório Institucional da UNESP
instname:Universidade Estadual Paulista (UNESP)
instacron:UNESP
instname_str Universidade Estadual Paulista (UNESP)
instacron_str UNESP
institution UNESP
reponame_str Repositório Institucional da UNESP
collection Repositório Institucional da UNESP
repository.name.fl_str_mv Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)
repository.mail.fl_str_mv
_version_ 1808129086091952128

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