A modified lightly doped drain mosfet for very large scale integration

Detalhes bibliográficos
Autor(a) principal: Bampi, Sergio
Data de Publicação: 1987
Tipo de documento: Tese
Idioma: eng
Título da fonte: Biblioteca Digital de Teses e Dissertações da UFRGS
Texto Completo: http://hdl.handle.net/10183/17967
Resumo: Reducing MOSFET dimensions while maintaining a constant supply voltage leads to higher electric fields inside the active regions of VLSI transistors. Operation of micron and submicron MOSFETs in the presence of high-field effects has required design innovations so that a constant supply voltage, acceptable punchthrough voltage, and long-term reliability are possible as device scaling continues. Drain engineering is necessary to cope with the susceptibility of MOSFETs to hot-carrier-related degradation. Reducing the electric fields at the drain end of the channel is critical to device reliability because degradation is related to carrier heating as they traverse regions with field strength in excess of 100 kV/cm. Optimized lightly doped drain (LDD) structures that spread the high electric field at the drain ensure the reliable 5 V operation of micron-sized n-channel MOSFETs. Recent experimental evidence revealed that LDDFETs are less reliable than conventional transistors if the n¯ region is too lightly doped. The JMOS transistor, a new n-MOS structure, is introduced to resolve the reliability problems in LDD devices with peak doping densities below 1 x 1018cm-³. A JFET is merged into the n-MOS structure to reduce the high fields under the gate. Two-dimensional simulations and experimental results demonstrate for the first time the operation of this device and its potential for VLSI applications requiring maximum supply voltage. A major experimental finding is that the JMOS can sustain 5 V operation even for submicron effective channel lengths because of the designer-controlled reduction of the maximum electrical field in the region under the gate traversed by carriers. The modification introduced in the LDD design is advantageous in terms of lower gate and substrate currents. Reliability can potentially be improved but at the expense of performance; however, the advantages of 5 V operation in micron-sized devices can outweigh this performance loss.
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spelling Bampi, SergioNão disponível2009-12-31T04:14:59Z1987http://hdl.handle.net/10183/17967000104774Reducing MOSFET dimensions while maintaining a constant supply voltage leads to higher electric fields inside the active regions of VLSI transistors. Operation of micron and submicron MOSFETs in the presence of high-field effects has required design innovations so that a constant supply voltage, acceptable punchthrough voltage, and long-term reliability are possible as device scaling continues. Drain engineering is necessary to cope with the susceptibility of MOSFETs to hot-carrier-related degradation. Reducing the electric fields at the drain end of the channel is critical to device reliability because degradation is related to carrier heating as they traverse regions with field strength in excess of 100 kV/cm. Optimized lightly doped drain (LDD) structures that spread the high electric field at the drain ensure the reliable 5 V operation of micron-sized n-channel MOSFETs. Recent experimental evidence revealed that LDDFETs are less reliable than conventional transistors if the n¯ region is too lightly doped. The JMOS transistor, a new n-MOS structure, is introduced to resolve the reliability problems in LDD devices with peak doping densities below 1 x 1018cm-³. A JFET is merged into the n-MOS structure to reduce the high fields under the gate. Two-dimensional simulations and experimental results demonstrate for the first time the operation of this device and its potential for VLSI applications requiring maximum supply voltage. A major experimental finding is that the JMOS can sustain 5 V operation even for submicron effective channel lengths because of the designer-controlled reduction of the maximum electrical field in the region under the gate traversed by carriers. The modification introduced in the LDD design is advantageous in terms of lower gate and substrate currents. Reliability can potentially be improved but at the expense of performance; however, the advantages of 5 V operation in micron-sized devices can outweigh this performance loss.application/pdfengMicroeletrônicaA modified lightly doped drain mosfet for very large scale integrationinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/doctoralThesisStanford Universitystanford, us1987doutoradoinfo:eu-repo/semantics/openAccessreponame:Biblioteca Digital de Teses e Dissertações da UFRGSinstname:Universidade Federal do Rio Grande do Sul (UFRGS)instacron:UFRGSTEXT000104774.pdf.txt000104774.pdf.txtExtracted Texttext/plain279663http://www.lume.ufrgs.br/bitstream/10183/17967/2/000104774.pdf.txt0c3e5b7f5f94946a8fdce54506c651fdMD52ORIGINAL000104774.pdf000104774.pdfTexto completo (inglês)application/pdf29150078http://www.lume.ufrgs.br/bitstream/10183/17967/1/000104774.pdf0c56db53b2e984adfafd67f1828ab35dMD51THUMBNAIL000104774.pdf.jpg000104774.pdf.jpgGenerated Thumbnailimage/jpeg1363http://www.lume.ufrgs.br/bitstream/10183/17967/3/000104774.pdf.jpg01459c6f7b46dfbdd795001d81abca3eMD5310183/179672021-05-07 04:32:48.77489oai:www.lume.ufrgs.br:10183/17967Biblioteca Digital de Teses e Dissertaçõeshttps://lume.ufrgs.br/handle/10183/2PUBhttps://lume.ufrgs.br/oai/requestlume@ufrgs.br||lume@ufrgs.bropendoar:18532021-05-07T07:32:48Biblioteca Digital de Teses e Dissertações da UFRGS - Universidade Federal do Rio Grande do Sul (UFRGS)false
dc.title.pt_BR.fl_str_mv A modified lightly doped drain mosfet for very large scale integration
title A modified lightly doped drain mosfet for very large scale integration
spellingShingle A modified lightly doped drain mosfet for very large scale integration
Bampi, Sergio
Microeletrônica
title_short A modified lightly doped drain mosfet for very large scale integration
title_full A modified lightly doped drain mosfet for very large scale integration
title_fullStr A modified lightly doped drain mosfet for very large scale integration
title_full_unstemmed A modified lightly doped drain mosfet for very large scale integration
title_sort A modified lightly doped drain mosfet for very large scale integration
author Bampi, Sergio
author_facet Bampi, Sergio
author_role author
dc.contributor.author.fl_str_mv Bampi, Sergio
dc.contributor.advisor1.fl_str_mv Não disponível
contributor_str_mv Não disponível
dc.subject.por.fl_str_mv Microeletrônica
topic Microeletrônica
description Reducing MOSFET dimensions while maintaining a constant supply voltage leads to higher electric fields inside the active regions of VLSI transistors. Operation of micron and submicron MOSFETs in the presence of high-field effects has required design innovations so that a constant supply voltage, acceptable punchthrough voltage, and long-term reliability are possible as device scaling continues. Drain engineering is necessary to cope with the susceptibility of MOSFETs to hot-carrier-related degradation. Reducing the electric fields at the drain end of the channel is critical to device reliability because degradation is related to carrier heating as they traverse regions with field strength in excess of 100 kV/cm. Optimized lightly doped drain (LDD) structures that spread the high electric field at the drain ensure the reliable 5 V operation of micron-sized n-channel MOSFETs. Recent experimental evidence revealed that LDDFETs are less reliable than conventional transistors if the n¯ region is too lightly doped. The JMOS transistor, a new n-MOS structure, is introduced to resolve the reliability problems in LDD devices with peak doping densities below 1 x 1018cm-³. A JFET is merged into the n-MOS structure to reduce the high fields under the gate. Two-dimensional simulations and experimental results demonstrate for the first time the operation of this device and its potential for VLSI applications requiring maximum supply voltage. A major experimental finding is that the JMOS can sustain 5 V operation even for submicron effective channel lengths because of the designer-controlled reduction of the maximum electrical field in the region under the gate traversed by carriers. The modification introduced in the LDD design is advantageous in terms of lower gate and substrate currents. Reliability can potentially be improved but at the expense of performance; however, the advantages of 5 V operation in micron-sized devices can outweigh this performance loss.
publishDate 1987
dc.date.issued.fl_str_mv 1987
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